MC9S12C128CFUE Freescale Semiconductor, MC9S12C128CFUE Datasheet - Page 255

• Manufacturer Part Number: MC9S12C128CFUE
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C128CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4000 B
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 61
• Number Of Timers: 1
• Operating Supply Voltage: - 0.3 V to + 6.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

9.3.2
This section describes in address order all the CRGV4 registers and their individual bits.
Freescale Semiconductor
CRGFLG
FORBYP
Register
COPCTL
CRGINT
CLKSEL
PLLCTL
RTICTL
REFDV
0x000A
0x0000
0x0001
0x0002
CTFLG
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
CTCTL
SYNR
Name
Register Descriptions
Register address = base address + address offset, where the base address is
defined at the MCU level and the address offset is defined at the module
level.
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
PLLSEL
WCOP
Bit 7
RTIF
RTIE
CME
0
0
0
0
0
0
= Unimplemented or Reserved
RSBCK
PLLON
PORF
Figure 9-3. CRG Register Summary
PSTP
RTR6
6
0
0
0
0
0
0
MC9S12C-Family / MC9S12GC-Family
SYSWAI
AUTO
SYN5
RTR5
LVRF
5
0
0
0
0
0
0
Rev 01.24
NOTE
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
ROAWAI
LOCKIF
LOCKIE
SYN4
RTR4
ACQ
4
0
0
0
0
0
REFDV3
PLLWAI
LOCK
SYN3
RTR3
3
0
0
0
0
0
0
REFDV2
TRACK
SYN2
CWAI
RTR2
PRE
CR2
2
0
0
0
0
REFDV1
RTIWAI
SCMIE
SCMIF
SYN1
RTR1
PCE
CR1
1
0
0
0
COPWAI
REFDV0
SCME
SYN0
RTR0
Bit 0
SCM
CR0
0
0
0
0
255