M30853FWGP#U5 Renesas Electronics America, M30853FWGP#U5 Datasheet - Page 127
![IC M32C MCU FLASH 100LQFP](/photos/12/22/122256/m30853fwgp_u5_sml.jpg)
M30853FWGP#U5
Manufacturer Part Number
M30853FWGP#U5
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FWGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
320KB (320K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FWGP#U5M30853FWGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30853FWGP#U5M30853FWGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R
R
e
E
v
MUL
[ Syntax ]
[ Operation ]
[ Function ]
[ Selectable src/dest ]*
[ Flag Change ]
[ Description Example ]
J
Chapter 3 Functions
*1 When the size specifier (.size) is (.B), indirect instruction addressing [src] and [dest] can be used in all addressing
*2 When you specify (.B) for the size specifier (.size), you cannot choose A0 and/or A1 for
1 .
0
Change
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0*
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM8/#IMM16/#IMM32
9
MUL.size
dest
dest
0 .
Flag
B
• This instruction multiplies
• When you selected (.B) for the size specifier (.size),
• When you selected (.W) for the size specifier (.size),
• When you selected (.L) for the size specifier (.size),
MUL.B
MUL.W
MUL.L
0
except R0L, R0H, R1L, R1H, and #IMM.
When the size specifier (.size) is (.W), indirect instruction addressing [src] can be used in all addressing
except R0, R1, and #IMM. Indirect instruction addressing [dest] cannot be used in any addressing.
When the size specifier (.size) is (.L), no indirect instruction addressing can be used.
simultaneously.
0
operation and the result is stored in 16 bits. When you specified an address register (A0, A1) for either
src
register, the 8 high-order bits become 0.
the operation and the result is stored in 32 bits. R0, R1, A0, and A1 can be selected for
specified R0 or R1 for
register is selected for
address register is selected for
operation and the result is stored in 32 bits. R2R0 is selected for
selected for
order bits are valid for the result.
3
1
2
9
0
0 -
or
0
U
6
1
0 .
dest
2
0
dest
dest
0
5
3 .
A1/A1/A1*
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
I
, operation is performed on the address register's 8 low-order bits. When
1
src,dest
A0,R0L
#3,R0
A0,R2R0
src
O
p
a
,
g
e
src
B
src
[src]
1
109
src
2
is zero-extended to be treated as 32-bit data for the operation, and only 32-low-
S
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
dest
dest
f o
src
3
Z
3
, the 24 low-order bits of the 32-bit operation result is stored. When the
, the result is stored in R2R0 or R3R1 accordingly. When the address
5
and
D
src
dest
, operation is performed using the 16 low-order bits of the register.
C
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
[dest]
[dest]
B , W , L
together including the sign bits and stores the result in
Signed multiply
MULtiple
; R0L and A0's 8 low-order bits are multiplied.
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0*
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
[dest]
[dest]
src
src
src
and
and
and
2
dest
dest
[ Instruction Code/Number of Cycles ]
src
[src]
dest
A1/A1/A1*
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
both are treated as 32-bit data for the
both are treated as 8-bit data for the
dest
both are treated as 16-bit data for
. When the address register is
dest
2
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
dest
dest
3.2 Functions
is the address
src
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
. When you
MUL
Page=
and
dest
dest
257
.
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