M30853FWGP#U5 Renesas Electronics America, M30853FWGP#U5 Datasheet - Page 138
![IC M32C MCU FLASH 100LQFP](/photos/12/22/122256/m30853fwgp_u5_sml.jpg)
M30853FWGP#U5
Manufacturer Part Number
M30853FWGP#U5
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FWGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
320KB (320K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FWGP#U5M30853FWGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30853FWGP#U5M30853FWGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R
R
e
E
v
PUSH
[ Syntax ]
[ Operation ]
[ Function ]
[ Selectable src ]
[ Flag Change ]
[ Description Example ]
J
*3 Indirect instruction addressing [src] can be used in all addressing except R0L/R0/R2R0, R0H/R2/-, R1L/
Chapter 3
Change
1 .
0
#IMM8/#IMM16/#IMM32
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0 A1/A1/A1
dsp:8[A0] dsp:8[A1]
dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:16[FB]
dsp:24[A0] dsp:24[A1] abs24
9
PUSH.size
• When the size specifier (.size) is (.B)
• When the size specifier (.size) is (.L)
Flag
0 .
B
• This instruction saves
• When (.W) is specified for the size specifier (.size) and
PUSH.B
PUSH.W
PUSH.L
R1/R3R1, R1H/R3/-, and #IMM.
0
M(SP)*
*1 The 8 high-order bits become undefined.
SP
M(SP)*
*2 When
SP
0
of the address register are the data to be operated on.
3
1
2
9
Even when (.B) is specified for the size specifier (.size) , SP is decreased by 2.
0
0 -
0
U
6
1
2
1
0 .
0
0
5
src
3 .
I
Functions
1
SP
src/[src]
SP
src/[src]
#5
#100H
R2R0
is address register(A0, A1), the 8 high-order bits become 0.
O
p
a
g
-
-
e
src
B
src*
120
2
4
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
S
src
3
f o
to the stack area.
Z
3
Save register/memory/immediate data
3
5
D
abs16
[A1]
dsp:8[FB]
C
B , W , L
• When the size specifier (.size) is (.W)
PUSH
M(SP)
SP
src
SP
src/[src]
is the address register, the 16 low-order bits
[ Instruction Code/Number of Cycles ]
-
2
3.2
PUSH
Page= 269
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