M30853FWGP#U5 Renesas Electronics America, M30853FWGP#U5 Datasheet - Page 346
![IC M32C MCU FLASH 100LQFP](/photos/12/22/122256/m30853fwgp_u5_sml.jpg)
M30853FWGP#U5
Manufacturer Part Number
M30853FWGP#U5
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FWGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
320KB (320K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FWGP#U5M30853FWGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30853FWGP#U5M30853FWGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Chapter 6
Figure 6.1.6. When executing an instruction to read from even addresses starting from an even address
1 .
0
9
0 .
B
Instructions
under execution
Address bus
Data bus (L)
0
Fetch code
Data bus (H)
Instruction
queue buffer
BCLK
0
RD
WR
3
Content at jump
address is prefetched at
the same time the
instruction queue buffer
is cleared.
1
2
9
0
0 -
0
6
Sample program
Address Code
FFC026
FFC026
FFC027
FFC028
FFC029
FFC02A
FFC02B
FFC02C
FFC02D
FFC02E
FFC02E
FFC032
FFC033
FFC034
FFC035
FFC036
FFC037
FFC038
FFC039
FFC03A
1
0 .
0
0
5
(Program area: 16-bit bus without wait state; Data area: 16-bit bus with wait state)
3 .
Calculation number of cycles
DR : Indicates a data read.
1
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
Jump address
p
: Indicates the locations of the instruction queue buffer that are cleared.
FFC02C FFC02E FFC030 FFC032
a
7A
DE
DE
DE
DE
DE
DE
DE
B9FB0020
7A
DE
DE
DE
DE
DE
DE
DE
g
7A
e
DE
DE
DE
DE
DE
DE
DE
JMP TEST_11
TEST_10:
TEST_11:
TEST_12:
328
DE
DE
P
f o
FB
B9
Instruction
3
P
FB
B9
3
JMP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MOV.W:G
JMP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
5
FB
B9
00
20
P
20
00
Fetch
B9FB
DE
7A
00
20
TEST_11
02000h,R1
TEST_12
DE
7A
P
Fetch
MOV.W
02000 FFC034 FFC036 FFC03A FFC03C
0020
DE
7A
DR
AA
AA
DE
DE
DE
7A
Content at address 2001
Content at address 2000
DE
DE
P
Fetch
7A
DE
DE
DE
DE
DE
JMP TEST_12
DE
DE
P
B9
FB
P
FB
B9
6.1 Instruction queue buffer
Content at jump address
is prefetched at the
same time the instruction
queue buffer is cleared.
16
16
FB
B9
00
20
P
20
00
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