M30853FWGP#U5 Renesas Electronics America, M30853FWGP#U5 Datasheet - Page 64
![IC M32C MCU FLASH 100LQFP](/photos/12/22/122256/m30853fwgp_u5_sml.jpg)
M30853FWGP#U5
Manufacturer Part Number
M30853FWGP#U5
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FWGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
320KB (320K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FWGP#U5M30853FWGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30853FWGP#U5M30853FWGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R
R
e
E
v
ADD
[ Syntax ]
[ Operation ]
[ Function ]
[ Selectable src/dest ]*
J
[ Flag Change ]
[ Description Example ]
Chapter 3
1 .
0
*1 Indirect instruction addressing [src] and [dest] can be used in all addressing except R0L/R0/R2R0, R0H/R2/-, R1L/
*2 When you specify (.B) for the size specifier (.size), you cannot choose A0 and/or A1 for
*3 Operation is performed on the stack pointer indicated by the U flag.
Change
Conditions
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0*
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM
9
ADD.size (:format)
dest
dest
0 .
Flag
B
O :
S :
Z :
C :
• This instruction adds
• When (.B) is specified for the size specifier (.size) and
• When (.W) is specified for the size specifier (.size) and
• When (.L) is specified for the size specifier (.size) and
• When (.L) is specified for the size specifier (.size) and
ADD.B
0
R1/R3R1, R1H/R3/-,
0
3
treated as 16-bit data for the operation. In this case, the 8 high-order bits become 0. Also, when
register, the 8 low-order bits of the address register are used as data to be operated on.
Also, when
as 32-bit data for the operation. The 24 low-order bits of the operation result are stored in
address register,
depending on the result of 32-bit operation.
the operation, and src is sign-extended to be treated as 32-bit data for the operation. The 24 low-order bits of the
operation result are stored in
1
2
9
0
0 -
0
U
T h e f l a g i s s e t w h e n a s i g n e d o p e r a t i o n r e s u l t e d i n e x c e e d i n g + 2 1 4 7 4 8 3 6 4 7 ( . L ) o r
-2147483648(.L), +32767 (.W) or -32768 (.W), or +127 (.B) or -128 (.B); otherwise cleared.
The flag is set when the operation resulted in MSB = 1; otherwise cleared.
The flag is set when the operation resulted in 0; otherwise cleared.
The flag is set when an unsigned operation resulted in exceeding +4294967295(.L) or +65535 (.W) or
+255 (.B); otherwise cleared.
6
1
2
0 .
0
0
dest
dest
5
3 .
I
A1/A1/A1*
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
Functions
src
1
[[A0]],abs16
O
p
is the address register, the 16 low-order bits of the address register are the data to be operated on.
+
+
a
g
src
e
B
SP/SP/SP
1
src
[src]
dest
is zero-extended to be treated as 32-bit data for the operation. The flags also change states
src
2
46
S
R0H/R2/-
R1H/R3/-
[A0]
abs24
dsp:8[SB]
dsp:16[SB] dsp:16[FB]
and
src,dest
f o
dest
3
Z
src
3
, and #IMM.
5
. The flags also change states depending on the result of 32-bit operation.
[dest]
[dest]
together and stores the result in
D
C
[A1]
dsp:8[FB]
abs16
Add without carry
G , Q , S (Can be specified)
B , W, L
[dest]
[dest]
ADDition
(See the next page for
dest
dest
dest
dest
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0*
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
SP/SP/SP*
+
+
is SP,
is the address register,
is the address register (A0, A1),
is the address register, the 8 high-order bits become 0.
src
[src]
dest
dest
2
3
is zero-extended to be treated as 32-bit data for
[ Instruction Code/Number of Cycles ]
.
A1/A1/A1*
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
src
/
dest
dest
dest
2
is zero-extended to be treated
abs24
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB] dsp:16[FB]
classified by format.)
src
dest
src
and
is zero-extended to be
. Also, when
dest
3.2
src
simultaneously.
is the address
[A1]
dsp:8[FB]
abs16
ADD
Page=
Functions
src
is the
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