M30853FWGP#U5 Renesas Electronics America, M30853FWGP#U5 Datasheet - Page 191
![IC M32C MCU FLASH 100LQFP](/photos/12/22/122256/m30853fwgp_u5_sml.jpg)
M30853FWGP#U5
Manufacturer Part Number
M30853FWGP#U5
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FWGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
320KB (320K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FWGP#U5M30853FWGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30853FWGP#U5M30853FWGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Chapter 4 Instruction Code
1 .
0
(4) Table of cycles
Content at start
Shows the number of cycles required to execute this instruction and the number of bytes in the instruc-
tion.
The number of cycles shown are the minimum possible, and they vary depending on the following conditions:
• Number of bytes that have been loaded in the instruction queue buffer
• Accessing of an external memory using 8-bit external bus
• Whether a wait is inserted in the bus cycle
Instruction bytes are indicated on the left side of the slash and execution cycles are indicated on the right side.
9
Contents at addresses following (start address of instruction + 2) are arranged as follows:
0 .
(1) Mnemonic
(2) Syntax
(3) Instruction code
B
Shows the mnemonic explained in this page.
Shows an instruction syntax using symbols.
Shows instruction code. Entered in ( ) are omitted depending on src/dest you selected.
address of
instruction
0
0
0000 0001 1 0 0 0 d4d3d2SIZEd1d0 1 1 1 1 1 1
b7
.size
3
.W
.B
1
2
Correspondence
9
0
0 -
0
6
SIZE
1
0 .
0
0
1
b0 b7
0
5
dsp16
abs16
#IMM16
abs24
dsp24
#IMM24
dsp8
#IMM8
3 .
1
address of instruc-
Content at (start
p
a
Rn
An
[An]
dsp:8[An]
g
e
tion+1)
b7
b7
b7
173
Low-order 8 bits
Low-order 8 bits
Correspondence
f o
dest
8 bits
3
R0L/R0/---
R1L/R1/---
R0H/R2/-
R1H/R3/-
A0
A1
[A0]
[A1]
dsp:8[A0]
dsp:8[A1]
3
+0
5
b0 b7
address of instruc-
Content at (start
b0
b0
b0
d4 d3 d2 d1 d0
1 0 0 1 0
1 0 0 1 1
1 0 0 0 0
1 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 0 0 0
0 0 0 0 1
0 0 1 0 0
0 0 1 0 1
tion+2)
b7
b7
High-order 8 bits
Middle-order 8bits
+1
Correspondence
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB/FB]
dsp:24[An]
abs16
abs24
b0
b0
b0
dest
(
b7
Contents at addresses following (start
dsp:8[SB]
dsp:8[FB]
dsp:16[A0]
dsp:16[A1]
dsp:16[SB]
dsp:16[FB]
dsp:24[A0]
dsp:24[A1]
abs16
abs24
High-order 8 bits
dsp8
dsp16/abs16
dsp24/abs24
address of instruction + 2)
(See the following figure.)
dest code
4.1
+2
d4 d3 d2 d1 d0
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 1
0 1 1 1 0
Guide to This Chapter
)
b0
#IMM8
#IMM16
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