M30853FWGP#U5 Renesas Electronics America, M30853FWGP#U5 Datasheet - Page 334
![IC M32C MCU FLASH 100LQFP](/photos/12/22/122256/m30853fwgp_u5_sml.jpg)
M30853FWGP#U5
Manufacturer Part Number
M30853FWGP#U5
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FWGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
320KB (320K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FWGP#U5M30853FWGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30853FWGP#U5M30853FWGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Chapter 5
Table 5.3.1 Interrupt Sequence Execution Time
*1 The vector table is fixed to even address.
*2 Allocate interrupt vector addresses in even addresses as must as possible.
*3 The high-speed interrupt is independent of these conditions.
Table 5.3.2 Relationship between Interrupts without Interrupt Priority Levels and IPL
1 .
0
_______
Peripheral I/O
INT instruction
NMI
Watchdog timer
Undefined instruction
Address match
Overflow
BRK instruction
(Variable vector table)
Single step
BRK2 instruction
BRK instruction
(Fixed vector table)
High-speed interrupt*
5.3.2 Changes of IPL When Interrupt Request Acknowledged
9
0 .
Interrupt sources without interrupt priority levels
Watchdog timer, NMI
Reset
Other
B
When an interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt is
set to the processor interrupt priority level (IPL).
If an interrupt request is acknowledged that does not have an interrupt priority level, the value shown in
Table 5.3.2 is set to the IPL.
0
0
3
1
2
9
0
0 -
0
Interrupt
6
1
0 .
0
0
5
3 .
Interrupt
1
p
a
_______
g
e
3
316
f o
3
Vector table is internal register
3
5
Interrupt vector address
Even address*
Even address*
Even address*
Odd address*
Odd address*
Odd address*
Even address
Even address
Even address
2
2
2
1
1
1
16 bits data bus
Value that is set to IPL
14 cycles
16 cycles
12 cycles
14 cycles
13 cycles
14 cycles
17 cycles
19 cycles
19 cycles
Not changed
7
0
5 cycles
5.3 Interrupt Sequence
8 bits data bus
16 cycles
16 cycles
14 cycles
14 cycles
15 cycles
16 cycles
19 cycles
19 cycles
21 cycles
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