C8051T633-GM Silicon Laboratories Inc, C8051T633-GM Datasheet - Page 103

• Manufacturer Part Number: C8051T633-GM
• Description: IC MCU 4KB 20PIN QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T63xr

Specifications of C8051T633-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: UART, SPI, SMBus
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4 x 16-bit
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051T630DK
• Minimum Operating Temperature: - 40 C
• For Use With: 336-1464 - KIT DEV FOR C8051T630 FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1461-5

19.2. Programmable Internal High-Frequency (H-F) Oscillator
All C8051T630/1/2/3/4/5 devices include a programmable internal high-frequency oscillator that defaults
as the system clock after a system reset. The internal oscillator period caPara1n be adjusted via the
OSCICL register as defined by SFR Definition 19.2.
On C8051T630/1/2/3/4/5 devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency.
The system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as
defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset.
19.2.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-
tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until one of the following events occur:




When one of the oscillator awakening events occur, the internal oscillator, CIP-51, and affected peripherals
resume normal operation, regardless of whether the event also causes an interrupt. The CPU resumes
execution at the instruction following the write to SUSPEND.
SFR Definition 19.2. OSCICL: Internal H-F Oscillator Calibration
SFR Address = 0xB3
Name
Reset
Bit
6:0 OSCICL[6:0] Internal Oscillator Calibration Bits.
Type
7
Bit
Port 0 Match Event.
Port 1 Match Event.
Comparator 0 enabled and output is logic 0.
Timer3 Overflow Event.
Unused
Name
R
7
0
Unused. Read = 0; Write = Don’t Care
These bits determine the internal oscillator period. When set to 0000000b, the H-F
oscillator operates at its fastest setting. When set to 1111111b, the H-F oscillator
operates at its slowest setting. The reset value is factory calibrated to generate an
internal oscillator frequency of 24.5 MHz.
Varies
6
Varies
5
Varies
Rev. 1.0
4
OSCICL[6:0]
Function
Varies
R/W
3
C8051T630/1/2/3/4/5
Varies
2
Varies
1
Varies
0
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