C8051T633-GM Silicon Laboratories Inc, C8051T633-GM Datasheet - Page 168
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C8051T633-GM
Manufacturer Part Number
C8051T633-GM
Description
IC MCU 4KB 20PIN QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T63xr
Specifications of C8051T633-GM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
UART, SPI, SMBus
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4 x 16-bit
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T630DK
Minimum Operating Temperature
- 40 C
For Use With
336-1464 - KIT DEV FOR C8051T630 FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1461-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051T633-GM
Manufacturer:
Silicon
Quantity:
270
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- Download datasheet (2Mb)
C8051T630/1/2/3/4/5
168
Parameter
Master Mode Timing (See Figure 23.8 and Figure 23.9)
T
T
T
T
Slave Mode Timing (See Figure 23.10 and Figure 23.11)
T
T
T
T
T
T
T
T
T
T
Note: T
MCKH
MCKL
MIS
MIH
SE
SD
SEZ
SDZ
CKH
CKL
SIS
SIH
SOH
SLH
SYSCLK
is equal to one period of the device system clock (SYSCLK).
Description
SCK High Time
SCK Low Time
MISO Valid to SCK Shift Edge
SCK Shift Edge to MISO Change
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
Last SCK Edge to MISO Change
(CKPHA = 1 ONLY)
Table 23.1. SPI Slave Timing Parameters
Rev. 1.0
1 x T
1 x T
1 x T
2 x T
2 x T
5 x T
5 x T
2 x T
2 x T
6 x T
SYSCLK
Min
—
—
—
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
0
+ 20
4 x T
4 x T
4 x T
8 x T
Max
—
—
—
—
—
—
SYSCLK
SYSCLK
—
—
—
—
SYSCLK
SYSCLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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