C8051T633-GM Silicon Laboratories Inc, C8051T633-GM Datasheet - Page 132
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C8051T633-GM
Manufacturer Part Number
C8051T633-GM
Description
IC MCU 4KB 20PIN QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T63xr
Specifications of C8051T633-GM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
UART, SPI, SMBus
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4 x 16-bit
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T630DK
Minimum Operating Temperature
- 40 C
For Use With
336-1464 - KIT DEV FOR C8051T630 FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1461-5
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Manufacturer
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Price
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Part Number:
C8051T633-GM
Manufacturer:
Silicon
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C8051T630/1/2/3/4/5
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 21.2 shows the min-
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “21.3.4. SCL Low Timeout” on page 129). The SMBus interface will force Timer 3 to
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 21.4).
132
Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
EXTHOLD
software acknowledgement, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
0
1
Table 21.2. Minimum SDA Setup and Hold Times
Minimum SDA Setup Time
1 system clock + s/w delay
T
low
11 system clocks
– 4 system clocks
or
Rev. 1.0
*
Minimum SDA Hold Time
12 system clocks
3 system clocks
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