MC908GR48ACFAE Freescale Semiconductor, MC908GR48ACFAE Datasheet - Page 144

• Manufacturer Part Number: MC908GR48ACFAE
• Description: IC MCU 48K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR48ACFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: ESCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 24-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1.5KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Input/Output (I/O) Ports
When bit DDRDx is a 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a 0,
reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
144
1. X = Don’t care
2. I/O pin pulled up to V
3. Writing affects data register, but does not affect input.
4. Hi-Z = High imp[edance
PTDPUE
Bit
X
1
0
DDRD
Bit
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
0
0
1
DD
READ DDRD ($0007)
WRITE DDRD ($0007)
WRITE PTD ($0003)
READ PTD ($0003)
by internal pullup device.
PTD
X
Bit
X
X
(1)
Input, Hi-Z
Input, V
Table 12-5. Port D Pin Functions
RESET
Figure 12-15. Port D I/O Circuit
I/O Pin
Output
Mode
DD
(2)
(4)
Table 12-5
Accesses to DDRD
DDRDx
PTDx
DDRD7–DDRD0
DDRD7–DDRD0
DDRD7–DDRD0
Read/Write
summarizes the operation of the port D pins.
PTDPUEx
PTD7–PTD0
Read
Pin
Pin
Accesses to PTD
V
DD
Freescale Semiconductor
INTERNAL
PULLUP
DEVICE
PTDx
PTD7–PTD0
PTD7–PTD0
PTD7–PTD0
Write
(3)
(3)