MC908GR48ACFAE Freescale Semiconductor, MC908GR48ACFAE Datasheet - Page 198
![IC MCU 48K FLASH 8MHZ 48-LQFP](/photos/12/27/122793/mc908gr48acfae_sml.jpg)
MC908GR48ACFAE
Manufacturer Part Number
MC908GR48ACFAE
Description
IC MCU 48K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR32ACFJE.pdf
(314 pages)
Specifications of MC908GR48ACFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
ESCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
24-ch x 10-bit
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1.5KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR48ACFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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System Integration Module (SIM)
14.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping
the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in CONFIG1. If SSREC
is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32. This is ideal
for applications using canned oscillators that do not require long startup times from stop mode.
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period.
14-20
198
shows stop mode recovery time from interrupt.
CGMXCLK
INT/BREAK
IAB
External crystal applications should use the full stop recovery time by
clearing the SSREC bit unless OSCENINSTOP bit is set in CONFIG2.
To minimize stop current, all pins configured as inputs should be driven to
a 1 or 0.
Note: Previous data can be operand data or the STOP opcode, depending on the last instruction.
CPUSTOP
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
R/W
IDB
IAB
Figure 14-20. Stop Mode Recovery from Interrupt
STOP ADDR
STOP +1
Figure 14-19. Stop Mode Entry Timing
PREVIOUS DATA
STOP ADDR + 1
STOP + 2
STOP RECOVERY PERIOD
NOTE
NOTE
NEXT OPCODE
Figure 14-19
STOP + 2
SAME
shows stop mode entry timing.
SP
SAME
SP – 1
SAME
SAME
Freescale Semiconductor
SP – 2
SP – 3
Figure
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