MC908GR48ACFAE Freescale Semiconductor, MC908GR48ACFAE Datasheet - Page 146

• Manufacturer Part Number: MC908GR48ACFAE
• Description: IC MCU 48K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR48ACFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: ESCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 24-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1.5KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Input/Output (I/O) Ports
RxD — SCI Receive Data Input
TxD — SCI Transmit Data Output
12.7.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a
1 to a DDRE bit enables the output buffer for the corresponding port E pin; a 0 disables the output buffer.
DDRE5–DDRE0 — Data Direction Register E Bits
Figure 12-19
When bit DDREx is a 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a 0,
reading address $0008 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
146
The PTE1/RxD pin is the receive data input for the ESCI module.
When the enable SCI bit, ENSCI, is clear, the ESCI module is disabled, and the PTE1/RxD pin is
available for general-purpose I/O. See
Module.
The PTE0/TxD pin is the transmit data output for the ESCI module. When the enable SCI bit, ENSCI,
is clear, the ESCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See
Chapter 13 Enhanced Serial Communications Interface (ESCI)
These read/write bits control port E data direction. Reset clears DDRE5–DDRE0, configuring all port
E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
shows the port E I/O logic.
Address:
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Reset:
Read:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
$000C
Bit 7
0
0
Figure 12-18. Data Direction Register E (DDRE)
= Unimplemented
6
0
0
DDRE5
Chapter 13 Enhanced Serial Communications Interface (ESCI)
5
0
Table 12-6
NOTE
DDRE4
4
0
summarizes the operation of the port E pins.
DDRE3
3
0
Module.
DDRE2
2
0
DDRE1
1
0
Freescale Semiconductor
DDRE0
Bit 0
0