M38507F8AFP#U1 Renesas Electronics America, M38507F8AFP#U1 Datasheet - Page 42

• Manufacturer Part Number: M38507F8AFP#U1
• Description: IC 740/3850 MCU FLASH 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38507F8AFP#U1

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 12.5 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: UART
• On-chip Adc: 9-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3850 Group (Spec.A QzROM version)
Rev.2.13
REJ03B0125-0213
Fig 46. State transitions of system clock
CM
CM
CM
CM
CM
CM
CM
CM
Notes1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
Middle-speed mode
7
6
5
4
7
6
5
4
Middle-speed mode
=0
=1
=0 (8 MHz oscillating)
=0 (32 kHz stopped)
=0
=1
=0 (8 MHz oscillating)
=1 (32 kHz oscillating)
(f(φ) = 1 MHz)
(f(φ) = 1 MHz)
Middle-speed mode
automatic switch set bit
“1”
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended.
3: Timer operates in the wait mode.
4: After STP instruction is released, the count source which had set by bit 2 (timer 12 count source selection bit) of the timer count source set register
5: Wait until oscillation stabilizes after oscillating the main clock X
6: When the mode is switched to the middle-speed mode by the middle-speed mode automatic switch set bit of MISRG, the waiting time set by the
7: The example assumes that 8 MHz is being applied to the X
at executing the STP instruction is supplied to timer 1. Accordingly, when bit 0 of MISRG is “0” and the timer 12 count source selection bit is “0”
(f(X
occurs automatically in the low-speed mode (at f(X
delay of approximately 16 ms occurs regardless of the operation mode.
middle-speed mode automatic switch wait time set bit is automatically generated, and then the mode is switched to the middle-speed mode.
Reset
Middle-speed mode
automatic switch start bit
“1”
Apr 17, 2009
IN
)/16 or f(X
CIN
)/16), a delay of approximately 1 ms occurs automatically in the high/middle-speed mode. A delay of approximately 256 ms
CM
“1”←→”0”
CM
“1”←→”0”
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6
6
CM
CM
CM
CM
CM
CM
CM
CM
CM
CM
CM
CM
CM
CM
CM
CM
7
6
5
4
7
6
5
4
7
6
5
4
7
6
5
4
High-speed mode
High-speed mode
=0
=0
=0 (8 MHz oscillating)
=0 (32 kHz stopped)
=0
=0
=0 (8 MHz oscillating)
=1 (32 kHz oscillating)
Low-speed mode
=1
=0
=0 (8 MHz oscillating)
=1 (32 kHz oscillating)
Low-speed mode
=1
=0
=1 (8 MHz stopped)
=1 (32 kHz oscillating)
IN
(f(φ) = 4 MHz)
(f(φ) = 16 kHz)
(f(φ) = 16 kHz)
(f(φ) = 4 MHz)
) = 8 MHz, f(X
IN
pin and 32 kHz to the X
IN
before the switching from the low-speed mode to middle/high-speed mode.
CIN
) = 32 kHz). When the timer 12 count source selection bit is “1” (f(X
b7
b4
CIN
CM
CM
CM
b7 b6
0 : I/O port function (stop oscillating)
1 : X
0 : Operating
1 : Stopped
0 0 : φ = f(X
0 1 : φ = f(X
1 0 : φ = f(X
1 1 : Not available
pin. φ indicates the internal clock.
4
5
7
, CM
: Port X
: Main clock (X
CIN-
6
X
: Main clock division ratio selection bit
COUT
CPU mode register
(CPUM : address 003B
C
IN
IN
CIN
switch bit
)/2 (High-speed mode)
)/8 (Middle-speed mode)
oscillating function
)/2 (Low-speed mode)
IN
-X
OUT
) stop bit
16
)
CIN
)), a