M38507F8AFP#U1 Renesas Electronics America, M38507F8AFP#U1 Datasheet - Page 59

• Manufacturer Part Number: M38507F8AFP#U1
• Description: IC 740/3850 MCU FLASH 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38507F8AFP#U1

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 12.5 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: UART
• On-chip Adc: 9-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
1.00
2.00
2.01
2.10
2.11
REVISION HISTORY
REVISION HISTORY
Dec. 10, 2004
Sep. 09, 2005
Nov. 14, 2005
Dec. 19, 2008
Oct. 13, 2005
Date
1,4-6,43
1, 4-6
54-59
Page
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38
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35
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1
5
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3
4
6
5
First edition issued
<Updating from Shortsheet (REJ03B0123-0100Z; Rev.1.00>
• Power source voltage is revised.
• Power dissipation is partly revised.
APPLICATION is partly deleted.
Table 2 is partly added. Note of Table 2 is added.
Delete the following: “PRELIMINARY”
Package name of 42P4B is revised. 42P4B → PRDP0042BA-A
Table 1 is partly revised.
Fig.3 is partly revised.
Table 4 is partly revised.
Notes on differences among 3850 group (standard), 3850 group (spec.H), and 3850 group
• ROM Code Protect Address (address FFDB
Fig.8 is partly revised.
Fig.9 is partly revised.
Table 7 is partly revised.
Fig.12 is partly revised.
WATCHDOG TIMER is revised.
Fig.38 is partly revised.
Oscillation Control (1) Stop mode is partly revised.
Reserved Area is revised. Reserved Area → Reserved Area, Reserved bit
The followings are added;
Flash Memory Version / QzROM Version is deleted.
Table 9 is partly revised.
PACKAGE OUTLINE of 42P4B is revised.
Note 1 of Table 2 is partly revised.
• ROM Code Protect Address (address FFDB
Notes On QzROM Writing Orders, Notes On ROM Code Protect are partly revised.
Fig 37. Block diagram of Watchdog timer;
QzROM version; approximately 1 k to 5 k Ω resistor → approximately 5 k Ω resistor
Package Outline is revised
Appendix added
Package name of 42P2R-A/E is revised. 42P2R-A/E → PRSP0042GA-A/B
Fig.8 is partly revised.
Initial value of watchdog timer is partly added.
When bit 7 of the watchdog timer control register is
“0”: 65.536ms at X
“1”: 256 µ s at X
3850 Group (Spec.A QzROM version) Data Sheet
IN
= 16MHz frequency. → 327.68 µ s at X
IN
= 16MHz frequency. → 83.886ms at X
(1/2)
Description
Summary
16
16
) is added.
) is partly revised.
IN
= 12.5 MHz frequency.
IN
= 12.5 MHz frequency.