M306N5FCTFP#U0 Renesas Electronics America, M306N5FCTFP#U0 Datasheet - Page 54

• Manufacturer Part Number: M306N5FCTFP#U0
• Description: IC M16C/6N MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N5FCTFP#U0

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Figure 6.2 PM1 Register
Processor Mode Register 1
NOTES:
b7
1. Rewrite this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).
2. For the mask ROM version, this bit is set to 0.
3. Effective when bits PM01 to PM00 are set to 01b (memory expansion mode) or 11b (microprocessor mode).
4. The PM12 bit is set to 1 by writing a 1 in a program. (writing a 0 has no effect.)
5. M16C/6N Group (M16C/6N5) has no device model expanded over 192 Kbytes of the internal ROM.
6. When the PM17 bit is set to 1 (with wait state), one wait state is inserted when accessing the internal RAM
Apr 14, 2006
b6
0 0
For the flash memory version, the PM10 bit controls whether block A is enabled or disabled. When the PM10
bit is set to 1, 0F000h to 0FFFFh (block A) can be used as internal ROM area.
In addition, the PM10 bit is automatically set to 1 while the FMR01 bit in the FMR0 register is set to 1 (CPU
rewrite mode).
Accrdingly, the PM13 bit is set to 0.
The PM13 bit is automatically set to 1 while the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode).
or internal ROM.
When the PM17 bit is set to 1 and accesses an external area, set the CSiW bit (i = 0 to 3) in the CSR register
to 0 (with wait state).
b5
b4
0
b3
0
b2
page 32 of 372
b1
b0
Bit Symbol
(b6-b4)
PM10
PM11
PM12
PM13
PM17
Symbol
-
PM1
(1)
CS2 area switch bit
(Data block enable bit)
Port P3_7 to P3_4 function
select bit
Watchdog timer function
select bit
Internal reserved area
expansion bit
Reserved bits
Wait bit
Address
Bit Name
(6)
0005h
(3)
(5)
(2)
0 : 08000h to 26FFFh (Block A disabled)
1 : 10000h to 26FFFh (Block A enabled)
0 : Address output
1 : Port function
0 : Watchdog timer interrupt
1 : Watchdog timer reset
Internal ROM area is:
0 : 192 Kbytes or smaller
1 : Expanded over 192 Kbytes
Set to 0
0 : No wait state
1 : With wait state (1 wait)
After Reset
00001000b
Function
(4)
6. Processor Mode
RW
RW
RW
RW
RW
RW
RW