M306N5FCTFP#U0 Renesas Electronics America, M306N5FCTFP#U0 Datasheet - Page 73

• Manufacturer Part Number: M306N5FCTFP#U0
• Description: IC M16C/6N MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N5FCTFP#U0

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Figure 8.5 PCLKR Register
Figure 8.6 CCLKR Register
CAN0 Clock Select Register
NOTES:
NOTE:
Peripheral Clock Select Register
1 0 0 0
b7
b7
0 0 0
1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).
2. Set to this bit after setting the C1CTLR register to 0020h, and set only when the Reset bit in the C0CTLR
3. Before setting this bit to 1, set the Sleep bit in the C0CTLR to 1 (sleep mode enabled).
1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).
Apr 14, 2006
b6
b6
register = 1 (reset/Initialization mode).
b5
b5
b4
0
b4
b3
0
b3
b2
0
b2
page 51 of 372
b1
b1
b0
b0
Bit Symbol
Bit Symbol
CCLK0
CCLK1
CCLK2
CCLK3
(b6-b4)
PCLK0
PCLK1
(b7-b2)
(b7)
Symbol
CCLKR
Symbol
PCLKR
-
-
-
(1)
CAN0 clock select bits
CAN0 CPU interface
sleep bit
Reserved bit
Reserved bit
Timers A, B, and A/D clock
select bit
(Clock source for timers A, B,
SI/O clock select bit
(Clock source for UART0 to UART2,
Reserved bits
(1)
SI/O3)
the dead time timer and A/D)
Bit Name
Address
(3)
025Fh
Bit Name
Address
025Eh
(2)
After Reset
0 0 0 No division
0 0 1 : Divide-by-2
0 1 0 : Divide-by-4
0 1 1 : Divide-by-8
1 0 0: Divide-by-16
1 0 1 :
1 1 0 :
1 1 1 :
0: CAN0 CPU interface operating
1: CAN0 CPU interface in sleep
Set to 0
Set to 1
b2 b1 b0
After Reset
00h
00h
0 : Divide-by-2 of fAD, f2
1 : fAD, f1
0 : f2SIO
1 : f1SIO
Set to 0
Do not set a value
Function
Function
8. Clock Generation Circuit
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW