M3087BFKGP#U3 Renesas Electronics America, M3087BFKGP#U3 Datasheet - Page 139
![IC M32C/87B MCU FLASH 144LQFP](/photos/12/31/123119/m3087bfkgp_u3_sml.jpg)
M3087BFKGP#U3
Manufacturer Part Number
M3087BFKGP#U3
Description
IC M32C/87B MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M3087BFKGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 115 of 587
Figure 11.5
11.6.2.1
11.6.2.2
Interrupt Control Register
b7 b6 b5 b4
Bits ILVL2 to ILVL0 determine an interrupt priority level. The higher the interrupt priority level is, the higher
priority the interrupt has.
When an interrupt request is generated, its interrupt priority level is compared to IPL. This interrupt is enabled
only when its interrupt priority level is higher than IPL. When bits ILVL2 to ILVL0 are set to 000b (level 0), the
interrupt is disabled.
The IR bit is automatically set to 1 (interrupt requested) by hardware when an interrupt request is generated.
After an interrupt request is acknowledged and an interrupt sequence in the corresponding interrupt vector is
executed, the IR bit is automatically set to 0 (interrupt not requested) by hardware.
The IR bit can be set to 0 by a program. Do not set it to 1.
NOTES:
1. When a 16-bit data bus is used in microprocessor mode and memory expansion mode, pins INT3 to INT5 are used as data bus.
2. The IR bit can be set to 0 only. (Do not set to 1.)
3. Set the POL bit to 0 when its corresponding bit in the IFSR register is set to 1 (both edges).
4. When the LVS bit is set to 1, set its corresponding bit in the IFSR register to 0 (one edge).
In this case, set bits ILVL2 to ILVL0 in registers INT3IC to INT5IC to 000b.
b3
b2
Bits ILVL2 to ILVL0
IR Bit
Interrupt Control Register (2/2)
b1
b0
Bit Symbol
(b7-b6)
ILVL0
ILVL1
ILVL2
POL
LVS
Symbol
INT0IC to INT2IC
INT3IC to INT5IC
IR
−
Interrupt priority level
select bits
Interrupt request bit
Polarity switch bit
Level sensitive/
edge sensitive switch bit
Unimplemented.
Write 0. Read as undefined value.
(1)
Bit Name
(3)
(2)
(4)
Address
009Eh, 007Eh, 009Ch
007Ch, 009Ah, 007Ah
b2 b1 b0
0 0 0: Level 0 (interrupt disabled)
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
1 0 1: Level 5
1 1 0: Level 6
1 1 1: Level 7
0: Interrupt not requested
1: Interrupt requested
0: Falling edge / "L" level selected
1: Rising edge / "H" level selected
0 : Edge sensitive
1 : Level sensitive
Function
After Reset
XX00 X000b
XX00 X000b
11. Interrupts
RW
RW
RW
RW
RW
RW
RW
−
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