M3087BFKGP#U3 Renesas Electronics America, M3087BFKGP#U3 Datasheet - Page 418
![IC M32C/87B MCU FLASH 144LQFP](/photos/12/31/123119/m3087bfkgp_u3_sml.jpg)
M3087BFKGP#U3
Manufacturer Part Number
M3087BFKGP#U3
Description
IC M32C/87B MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M3087BFKGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Manufacturer
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 394 of 587
Figure 22.57
Group 2 SI/O Communication Mode Register
b7 b6 b5 b4
NOTES:
1. When changing mode, set bits GMD1 and GMD0 to 00b (communication unit is reset) and wait for one or more fBT2 clock
2. Set bits GMD1 and GMD0 to 01b (clock synchronous mode) or 10b (IE mode) while fBT2 is stopped.
cycles before setting to different mode.
b3
G2MR Register
b2
b1
b0
Bit Symbol
UFORM
CKDIR
(b5-b3)
GMD0
GMD1
IRS
Symbol
G2MR
−
Communication mode
select bits
Clock select bit
Unimplemented.
Write 0. Read as undefined value.
Bit order select bit
Transmit interrupt
source select bit
Bit Name
Address
016Ah
22. Intelligent I/O (Group 2 Communication Function)
b1 b0
0 0 : Communication unit is reset
0 1 : Clock synchronous mode
1 0 : IE mode
1 1 : Do not set to this value
0 : Internal clock
1 : External clock
0 : LSB first
1 : MSB first
0 : No data in the G2TB register (TI = 1)
1 : Transmit operation completed
(TXEPT = 1)
(The OER bit becomes 0)
(2)
Function
(2)
(1)
After Reset
00XX X000b
RW
RW
RW
RW
RW
RW
−
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