M3087BFKGP#U3 Renesas Electronics America, M3087BFKGP#U3 Datasheet - Page 563
![IC M32C/87B MCU FLASH 144LQFP](/photos/12/31/123119/m3087bfkgp_u3_sml.jpg)
M3087BFKGP#U3
Manufacturer Part Number
M3087BFKGP#U3
Description
IC M32C/87B MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M3087BFKGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 539 of 587
Figure 27.5
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
WR,WRL,WRH
Read Timing (1 φ + 1 φ Bus Cycle)
Write Timing (1 φ + 1 φ Bus Cycle)
BCLK
BCLK
BHE
BHE
ADi
ADi
CSi
RD
DBi
CSi
DBi
NOTES:
NOTES:
1. Values guaranteed only when the MCU is used stand-alone.
2. Varies with operation frequency:
3. Varies with operation frequency:
A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK).
td(DB-WR) = (tcyc x m - 20) ns.min
th(WR-DB) = (tcyc / 2 - 15) ns.min
th(WR-AD) = (tcyc / 2 - 10) ns.min
th(WR-CS) = (tcyc / 2 - 10) ns.min
tw(WR) = (tcyc / 2 x n - 15) ns.min
td(BCLK-AD)
td(BCLK-AD)
tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a φ + b φ , m = (b x 2) + 1)
tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle a φ + b φ , n = a + b)
VCC1 = VCC2 = 5 V Timing Diagram (3/4)
(if external bus cycle a φ + b φ , n = (b x 2) - 1)
18ns.max
td(BCLK-RD)
18ns.max
td(BCLK-CS)
18ns.max
td(BCLK-CS)
18ns.max
( if external bus cycle a φ + b φ , m = b)
tcyc
tcyc
(1)
(1)
td(BCLK-WR)
18ns.max
Hi-Z
18ns.max
tac1(AD-DB)
tac1(RD-DB)
td(DB-WR)
(2)
tsu(DB-BCLK)
26ns.min
tw(WR)
(3)
(2)
(1)
(3)
th(WR-DB)
th(WR-AD)
Measurement Conditions:
- VCC1 = VCC2 = 4.2 to 5.5 V
- Input high and low voltage: VIH = 2.5 V, VIL = 0.8 V
- Output high and low voltage: VOH = 2.0 V, VOL = 0.8 V
th(WR-CS)
th(BCLK-WR)
-5ns.min
tcyc=
(3)
(3)
(3)
th(BCLK-CS)
-3ns.min
th(BCLK-AD)
-3ns.min
th(BCLK-RD)
-5ns.min
th(BCLK-AD)
-3ns.min
th(BCLK-CS)
-3ns.min
f(BCLK)
th(RD-CS)
0ns.min
th(RD-AD)
0ns.min
th(RD-DB)
0ns.min
10
9
VCC1=VCC2=5V
27. Electrical Characteristics
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