M3087BFKGP#U3 Renesas Electronics America, M3087BFKGP#U3 Datasheet - Page 392
![IC M32C/87B MCU FLASH 144LQFP](/photos/12/31/123119/m3087bfkgp_u3_sml.jpg)
M3087BFKGP#U3
Manufacturer Part Number
M3087BFKGP#U3
Description
IC M32C/87B MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M3087BFKGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number
Manufacturer
Quantity
Price
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 22. Intelligent I/O (Group 0 and 1 Communication Function)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 368 of 587
22.4
Figure 22.36
Reception
Transmission
In the group 0 communication function, clock synchronous mode or HDLC data processing mode is available. In
the group 1 communication function, clock synchronous mode, clock asynchronous (UART) mode, or HDLC data
processing mode is available. Figure 22.36 shows a block diagram of group 0 communication function. Figure
22.37 shows a block diagram of group 1 communication function. Figures 22.38 to 22.46 show registers associated
with the communication function.
Clock input to
ISCLK0 pin
i = 0 to 3
CCS1 and CCS0: bits in the CCS register
CKDIR: bit in the G0MR register
TXSL, RXSL: bits in the G0EMR register
SIO0TR, G0TOR: bits in the IIO1IR register
SIO0RR, G0RIR: bits in the IIO0IR register
Group 0 and Group 1 Communication Function
Receive data
input to
ISRXD0 pin
Group 0 Communication Function Block Diagram
j = 0, 1
f2n
CCS1 and CCS0
f1
f8
01
10
11
0
1
CKDIR
Polarity
invert
register
Transmit
register
G0RI
Shift
G0TB
shift
Control
Clock
0
1
RXSL
G0CMPi
G1CMPi
G1CMPi
G1CMPi
Bit insert
Comparator
circuit
register
G0DR
Latch
Shift
G0MSKj
G1MSKi
Transmission
control circuit
Reception control
Bit delete
calculation
verifying
circuit
circuit
CRC
TXSL
Transmit interrupt request
(SIO0TR)
HDLC data transmit interrupt
request (G0TOR)
0
1
Serial clock output from
ISCLK0 pin
Polarity
calculation
invert
register
Receive
G0TO
register
Shift
G0RB
circuit
Receive complete
interrupt request
HDLC data receive
Interrupt request
shift
CRC
(SIO0RR)
Transmit data
output from
ISTXD0 pin
(G0RIR)
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