AT90PWM316-16MU Atmel, AT90PWM316-16MU Datasheet - Page 244

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AT90PWM316-16MU

Manufacturer Part Number
AT90PWM316-16MU
Description
MCU AVR 16K FLASH 16MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet

Specifications of AT90PWM316-16MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-QFN
Processor Series
AT90PWMx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Cpu Family
90P
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
1KB
# I/os (max)
53
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
QFN EP
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOICATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
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21.6.3
21.6.4
244
AT90PWM216/316
Offset Compensation Schemes
ADC Accuracy Definitions
The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential mea-
surements as much as possible. The remaining offset in the analog path can be measured
directly by shortening both differential inputs using the AMPxIS bit with both inputs unconnected.
(See “Amplifier 0 Control and Status register – AMP0CSR” on page 256.
1Control and Status register – AMP1CSR” on page
tracted in software from the measurement results. Using this kind of software based offset
correction, offset on any channel can be reduced below one LSB.
An n-bit single-ended ADC converts a voltage linearly between GND and V
(LSBs). The lowest code is read as 0, and the highest code is read as 2
Several parameters describe the deviation from the ideal behavior:
Figure 21-10. Offset Error
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last
(at 0.5 LSB). Ideal value: 0 LSB.
transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).
Ideal value: 0 LSB
Output Code
Offset
Error
257.). This offset residue can be then sub-
V
REF
Input Voltage
n
-1.
and
Ideal ADC
Actual ADC
REF
See “Amplifier
7710E–AVR–08/10
in 2
n
steps

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