AT90PWM316-16MU Atmel, AT90PWM316-16MU Datasheet - Page 35

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AT90PWM316-16MU

Manufacturer Part Number
AT90PWM316-16MU
Description
MCU AVR 16K FLASH 16MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet

Specifications of AT90PWM316-16MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-QFN
Processor Series
AT90PWMx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Cpu Family
90P
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
1KB
# I/os (max)
53
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
QFN EP
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOICATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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7.6.2
7710E–AVR–08/10
PLL Control and Status Register – PLLCSR
Figure 7-3.
• Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM216/316 and always read as zero.
• Bit 2 – PLLF: PLL Factor
The PLLF bit is used to select the division factor of the PLL.
If PLLF is set, the PLL output is 64Mhz.
If PLLF is clear, the PLL output is 32Mhz.
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is
started as PLL reference clock. If PLL is selected as a system clock source the value for this bit
is always 1.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable
CLK
Bit
$29 ($29)
Read/Write
Initial Value
PLL
XTAL1
XTAL2
for PSC. After the PLL is enabled, it takes about 100 ms for the PLL to lock.
RC OSCILLATOR
OSCCAL
8 MHz
PCK Clocking System AT90PWM216/316
OSCILLATORS
R
7
0
R
6
0
CKSEL3..0
R
5
0
DIVIDE
BY 8
R
4
0
PLLE
PLL
64x
R
3
0
Detector
Lock
DIVIDE
DIVIDE
PLLF
PLLF
BY 2
BY 4
R/W
AT90PWM216/316
2
0
PLLE
R/W
0/1
1
PLOCK
CLK
PLOCK
R
0
0
CK
PLL
SOURCE
PLLCSR
35

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