AT90PWM3-16SQ Atmel, AT90PWM3-16SQ Datasheet - Page 339

• Manufacturer Part Number: AT90PWM3-16SQ
• Description: IC AVR MCU FLASH 8K 32SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM3-16SQ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-SOIC (7.5mm Width)
• Processor Series: AT90PWMx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• On-chip Dac: 10 bit, 1 Channel
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOICATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATSTK520 - ADAPTER KIT FOR 90PWM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

29. Instruction Set Summary
4317J–AVR–08/10
Mnemonics
FMULSU
MULSU
FMULS
RCALL
BREQ
BRCC
BRGE
BRHC
ADIW
MULS
FMUL
RJMP
ICALL
CPSE
SBRC
SBRS
BRBS
BRBC
BRNE
BRCS
BRSH
BRLO
BRPL
BRHS
BRTS
BRTC
BRVS
BRVC
SBIW
BRMI
BRLT
SUBI
SBCI
ANDI
COM
IJMP
RETI
SBIC
SBIS
BRIE
BRID
ADD
ADC
SUB
SBC
AND
EOR
NEG
SBR
CBR
DEC
CLR
SER
MUL
RET
CPC
TST
ORI
INC
CPI
OR
CP
Operands
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rdl,K
Rd, K
Rd, K
Rdl,K
Rd, K
Rd, K
Rd,Rr
Rd,Rr
Rd,Rr
Rd,K
Rd,K
Rd,K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
Rd
Rd
Rd
Rd
Rd
Rd
Rd
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
Fractional Multiply Signed with Unsigned
Subtract with Carry Constant from Reg.
Logical AND Register and Constant
Branch if Greater or Equal, Signed
Logical OR Register and Constant
Compare Register with Immediate
Branch if Overflow Flag is Cleared
Branch if Less Than Zero, Signed
Subtract with Carry two Registers
Branch if Half Carry Flag Cleared
Skip if Bit in I/O Register Cleared
Subtract Constant from Register
Subtract Immediate from Word
Skip if Bit in I/O Register is Set
Multiply Signed with Unsigned
Branch if Overflow Flag is Set
Add with Carry two Registers
Skip if Bit in Register Cleared
Branch if Status Flag Cleared
Branch if Half Carry Flag Set
Fractional Multiply Unsigned
Branch if Interrupt Disabled
Skip if Bit in Register is Set
Branch if Interrupt Enabled
Fractional Multiply Signed
Branch if Same or Higher
Branch if Status Flag Set
Relative Subroutine Call
Branch if T Flag Cleared
Add Immediate to Word
Exclusive OR Registers
Branch if Carry Cleared
Compare, Skip if Equal
Subtract two Registers
Logical AND Registers
Clear Bit(s) in Register
Test for Zero or Minus
Logical OR Registers
Set Bit(s) in Register
Compare with Carry
Branch if T Flag Set
One’s Complement
Two’s Complement
Indirect Jump to (Z)
Branch if Not Equal
Branch if Carry Set
Add two Registers
Indirect Call to (Z)
Subroutine Return
Multiply Unsigned
Interrupt Return
Branch if Lower
Multiply Signed
Branch if Equal
Branch if Minus
Description
Clear Register
Relative Jump
Branch if Plus
Set Register
Decrement
Increment
Compare
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
if (Rd = Rr) PC ← PC + 2 or 3
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
Rdh:Rdl ← Rdh:Rdl + K
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • (0xFF - K)
Rd ← Rd + Rr + C
PC ← PC + k + 1
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
Rd ← Rd - Rr - C
Rd ← 0xFF − Rd
PC ← PC + k + 1
Rd ← 0x00 − Rd
Rd ← Rd - K - C
Rd ← Rd ⊕ Rd
Rd ← Rd ⊕ Rr
Rd ← Rd • Rd
Rd ← Rd + Rr
Rd ← Rd • Rr
Rd ← Rd v Rr
PC ← STACK
PC ← STACK
Rd ← Rd - Rr
Rd ← Rd • K
Rd ← Rd v K
Rd ← Rd v K
Rd ← Rd + 1
Rd ← Rd − 1
Rd ← Rd - K
Operation
Rd − Rr − C
Rd ← 0xFF
PC ← Z
PC ← Z
Rd − Rr
Rd − K
AT90PWM2/3/2B/3B
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V
Flags
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z,C
Z,C
Z,C
Z,C
Z,C
Z,C
I
#Clocks
1/2/3
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
3
3
4
4
1
1
1
339