AT90PWM3-16SQ Atmel, AT90PWM3-16SQ Datasheet - Page 75

• Manufacturer Part Number: AT90PWM3-16SQ
• Description: IC AVR MCU FLASH 8K 32SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM3-16SQ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-SOIC (7.5mm Width)
• Processor Series: AT90PWMx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• On-chip Dac: 10 bit, 1 Channel
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOICATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATSTK520 - ADAPTER KIT FOR 90PWM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4317J–AVR–08/10
XCK, USART External clock. The Data Direction Register (DDD0) controls whether the clock is
output (DDD0 set) or input (DDD0 cleared). The XCK0 pin is active only when the USART oper-
ates in Synchronous mode.
SS_A: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDD0. As a slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDD0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTD0 bit.
Table 11-10
shown in
Table 11-10. Overriding Signals for Alternate Functions PD7..PD4
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Figure 11-5 on page
and
Table 11-11
PD7/
ACMP0
0
0
0
0
0
0
ACMP0D
0
–
ACOMP0
relates the alternate functions of Port D to the overriding signals
66.
PD6/ADC3/
ACMPM/INT0
0
0
0
0
0
0
ADC3D + In0en
In0en
INT0
ADC3
ACMPM
PD5/ADC2/
ACMP2
0
0
0
0
0
ADC2D
0
ADC2
ACOMP2
0
AT90PWM2/3/2B/3B
PD4/ADC1/RXD/
ICP1A/SCK_A
RXEN + SPE •
MSTR • SPIPS
PD4 •
PUD
RXEN + SPE •
MSTR • SPIPS
0
SPE • MSTR •
SPIPS
–
ADC1D
0
ICP1A
ADC1
75