ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet - Page 100

• Manufacturer Part Number: ATTINY24-15SSZ
• Description: MCU AVR 2K FLASH 15MHZ 14-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15SSZ

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.7.1
14.7.2
14.7.3
100
Atmel ATtiny24/44/84 [Preliminary]
Force Output Compare
Compare Match Blocking by TCNT1 Write
Using the Output Compare Unit
The OCR1x register is double buffered when using any of the twelve pulse width modulation
(PWM) modes. For the normal and clear timer on compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCR1x
compare register to either top or bottom of the counting sequence. The synchronization pre-
vents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCR1x register access may seem complex, but this is not the case. When the double
buffering is enabled, the CPU has access to the OCR1x buffer register, and if double buffering
is disabled the CPU will access the OCR1x directly. The content of the OCR1x (buffer or com-
pare) register is changed only by a write operation (the timer/counter does not update this
register automatically as it does for the TCNT1 and ICR1 registers). Therefore, OCR1x is not
read via the high byte temporary register (TEMP). However, it is a good practice to read the
low byte first, as when accessing other 16-bit registers. Writing the OCR1x registers must be
done via the TEMP register because the compare of all 16 bits is done continuously. The high
byte (OCR1xH) has to be written first. When the high byte I/O location is written by the CPU,
the TEMP register will be updated by the value written. Then when the low byte (OCR1xL) is
written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the
OCR1x buffer or the OCR1x compare register in the same system clock cycle.
For more information of how to access the 16-bit registers, refer to
ters” on page
In non-PWM waveform generation modes, the match output of the comparator can be forced
by writing a logical one to the Force Output Compare (1x) bit. Forcing compare match will not
set the OCF1x flag or reload/clear the timer, but the OC1x pin will be updated as if a real com-
pare match had occurred (the COM11:0 bit settings define whether the OC1x pin is set,
cleared or toggled).
All CPU writes to the TCNT1 Register will block any compare match that occurs in the next
timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized
to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is
enabled.
Because writing TCNT1 in any mode of operation will block all compare matches for one timer
clock cycle, there are risks involved in changing TCNT1 when using any of the output compare
channels, independent of whether the timer/counter is running or not. If the value written to
TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect
waveform generation. Do not write the TCNT1 equal to top in PWM modes with variable top
values. The compare match for the top will be ignored, and the counter will continue to
0xFFFF. Similarly, do not write the TCNT1 value equal to bottom when the counter is
down-counting.
The setup of the OC1x should be performed before setting the data direction register for the
port pin to output. The easiest way of setting the OC1x value is to use the force output com-
pare (1x) strobe bits in normal mode. The OC1x register keeps its value even when changing
between waveform generation modes.
93.
“Accessing 16-bit Regis-
7701D–AVR–09/10