ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet - Page 72

• Manufacturer Part Number: ATTINY24-15SSZ
• Description: MCU AVR 2K FLASH 15MHZ 14-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15SSZ

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.2.2
13.3
13.4
72
Timer/Counter Clock Sources
Counter Unit
Atmel ATtiny24/44/84 [Preliminary]
Definitions
Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when
no clock source is selected. The output from the Clock Select logic is referred to as the timer
clock (clk
The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform
Generator to generate a PWM or variable frequency output on the Output Compare pins
(OC0A and OC0B). See
event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an
Output Compare interrupt request.
Many register and bit references in this section are written in general form. A lower case "n"
replaces the timer/counter number, in this case 0. A lower case "x" replaces the output com-
pare unit, in this case compare unit A or compare unit B. However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing timer/coun-
ter 0 counter value and so on.
The definitions in
Table 13-1.
The Timer/Counter can be clocked by an internal or an external clock source. The clock
source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0)
bits located in the Timer/Counter Control Register (TCCR0B). For details on clock sources
and prescaler, see
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
ure 13-2 on page 72
Figure 13-2. Counter Unit Block Diagram
BOTTOM
MAX
TOP
T0
).
DATA BUS
Definitions
The counter reaches the BOTTOM when it becomes 0x00.
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest value in
the count sequence. The TOP value can be assigned to be the fixed value
0xFF (MAX) or the value stored in the OCR0A Register. The assignment is
dependent on the mode of operation.
TCNTn
Table 13-1 on page 72
“Timer/Counter Prescaler” on page
shows a block diagram of the counter and its surroundings.
“Output Compare Unit” on page 73
direction
count
clear
bottom
are also used extensively throughout the document.
Control Logic
top
TOVn
(Int.Req.)
clk
119.
Tn
for details. The Compare Match
Clock Select
( From Prescaler )
Detector
Edge
7701D–AVR–09/10
Tn
Fig-