ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet - Page 80

• Manufacturer Part Number: ATTINY24-15SSZ
• Description: MCU AVR 2K FLASH 15MHZ 14-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15SSZ

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

80
Atmel ATtiny24/44/84 [Preliminary]
Figure 13-7. Phase Correct PWM Mode, Timing Diagram
The timer/counter overflow flag (TOV0) is set each time the counter reaches bottom. The inter-
rupt flag can be used to generate an interrupt each time the counter reaches the bottom value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0x1:0 bits to three. Setting the COM0A0
bits to one allows the OC0A pin to toggle on compare matches if the WGM02 bit is set. This
option is not available for the OC0B pin (See
will only be visible on the port pin if the data direction for the port pin is set as output. The
PWM waveform is generated by clearing (or setting) the OC0x register at the compare match
between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x
register at compare match between OCR0x and TCNT0 when the counter decrements. The
PWM frequency for the output when using phase correct PWM can be calculated by the fol-
lowing equation:
The variable N represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to bottom, the
output will be continuously low, and if set equal to max the output will be continuously high for
non-inverted PWM mode. For inverted PWM, the output will have the opposite logic values.
At the very start of period 2 in
even though there is no compare match. The point of this transition is to guarantee symmetry
around bottom. There are two cases that give a transition without a compare match.
TCNTn
OCn
OCn
Period
1
Figure 13-7 on page 80
f
OCnxPCPWM
2
Table 13-4 on page
=
-------------------- -
N
f
clk_I/O
510
OCn has a transition from high to low
3
84). The actual OC0x value
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
(COMnx1:0 = 2)
(COMnx1:0 = 3)
7701D–AVR–09/10