ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet - Page 128

• Manufacturer Part Number: ATTINY24-15SSZ
• Description: MCU AVR 2K FLASH 15MHZ 14-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15SSZ

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3.5
16.3.6
16.4
16.4.1
16.4.2
16.4.3
16.4.4
16.4.5
128
Alternative USI Usage
Atmel ATtiny24/44/84 [Preliminary]
Start Condition Detector
Clock speed considerations
Half-duplex Asynchronous Data Transfer
4-bit Counter
12-bit Timer/Counter
Edge-Triggered External Interrupt
Software Interrupt
The start condition detector is shown in
the range of 50 to 300ns) to ensure valid sampling of the SCL line. The start condition detector
is only enabled in two-wire mode.
The start condition detector is working asynchronously, and can, therefore, wake up the pro-
cessor from the power-down sleep mode. However, the protocol used might have restrictions
on the SCL hold time. Therefore, when using this feature in this case, the oscillator start-up
time set by the CKSEL fuses (see
also be taken into consideration. See the USISIF bit description in
ister” on page 129
Maximum frequency for SCL and SCK is f
receive rate in both two- and three-wire mode. In two-wire slave mode the two-wire clock con-
trol unit will hold SCL low until the slave is ready to receive more data. This may reduce the
actual data rate in two-wire mode.
When the USI unit is not used for serial communication, it can be set up to do alternative tasks
due to its flexible design.
By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact
and higher performance UART than by software only.
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will generate an increment.
Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit
counter.
By setting the counter to maximum value (F), it can function as an additional external interrupt.
The overflow flag and interrupt enable bit are then used for the external interrupt. This feature
is selected by the USICS1 bit.
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
for further details.
“Clock Systems and their Distribution” on page
Figure 16-6 on page
CK
/4. This is also the maximum data transmit and
127. The SDA line is delayed (in
“USISR – USI Status Reg-
7701D–AVR–09/10
25) must