PIC18F8310-E/PT Microchip Technology, PIC18F8310-E/PT Datasheet - Page 146

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PIC18F8310-E/PT

Manufacturer Part Number
PIC18F8310-E/PT
Description
IC PIC MCU FLASH 8KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F8310-E/PT

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F8310-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F6310/6410/8310/8410
11.9
PORTJ is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISJ. Setting a
TRISJ bit (= 1) will make the corresponding PORTJ pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISJ bit (= 0) will
make the corresponding PORTJ pin an output (i.e., put
the contents of the output latch on the selected pin).
The Output Latch register (LATJ) is also memory
mapped. Read-modify-write operations on the LATJ
register, read and write the latched output value for
PORTJ.
All pins on PORTJ are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
DS39635C-page 146
Note:
Note:
PORTJ, TRISJ and
LATJ Registers
PORTJ
PIC18F8310/8410 devices.
On a Power-on Reset, these pins are
configured as digital inputs.
is
available
only
on
When the external memory interface is enabled, all of
the PORTJ pins function as control outputs for the
interface. This occurs automatically when the interface
is enabled by clearing the EBDIS control bit
(MEMCON<7>). The TRISJ bits are also overridden.
EXAMPLE 11-9:
CLRF
CLRF
MOVLW 0xCF
MOVWF TRISJ
PORTJ
LATJ
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as output
; RJ7:RJ6 as inputs
INITIALIZING PORTJ
 2010 Microchip Technology Inc.

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