PIC18F8310-E/PT Microchip Technology, PIC18F8310-E/PT Datasheet - Page 189

• Manufacturer Part Number: PIC18F8310-E/PT
• Description: IC PIC MCU FLASH 8KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8310-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

REGISTER 17-5:
 2010 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
bit 7
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit;
0 = Acknowledge sequence Idle
RCEN: Receive Enable bit (Master mode only)
1 = Enables Receive mode for I
0 = Receive Idle
PEN: Stop Condition Enable bit (Master mode only)
1 = Initiate Stop condition on SDA and SCL pins; automatically cleared by hardware
0 = Stop condition Idle
RSEN: Repeated Start Condition Enable bit (Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins; automatically cleared by hardware.
0 = Repeated Start condition Idle
SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins; automatically cleared by hardware
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
SSPCON2: MSSP CONTROL REGISTER 2 (I
GCEN
R/W-0
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
a receive.
If the I
may not be written (or writes to the SSPBUF are disabled).
automatically cleared by hardware
2
C module is not in Idle mode, this bit may not be set (no spooling) and the SSPBUF
ACKSTAT ACKDT
R/W-0
PIC18F6310/6410/8310/8410
R/W-0
2
(1)
C
ACKEN
R/W-0
(2)
(2)
(2)
RCEN
R/W-0
(2)
2
C™ MODE)
(2)
(1)
PEN
R/W-0
(2)
(2)
(2)
RSEN
R/W-0
DS39635C-page 189
(2)
SEN
R/W-0
bit 0
(2)