PIC18F8310-E/PT Microchip Technology, PIC18F8310-E/PT Datasheet - Page 388

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PIC18F8310-E/PT

Manufacturer Part Number
PIC18F8310-E/PT
Description
IC PIC MCU FLASH 8KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F8310-E/PT

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F8310-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F6310/6410/8310/8410
FIGURE 27-24:
TABLE 27-26: A/D CONVERSION REQUIREMENTS
DS39635C-page 388
130
131
132
135
137
Note 1:
Param
No.
A/D CLK
Note 1:
A/D DATA
SAMPLE
2:
3:
4:
ADRES
BSF ADCON0, GO
T
T
T
T
T
Symbol
ADIF
AD
CNV
ACQ
SWC
DIS
2:
GO
Q4
The time of the A/D clock period is dependent on the device frequency and the T
ADRES register may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AV
50.
On the following cycle of the device clock.
(1)
If the A/D clock source is selected as RC, a time of T
This allows the SLEEP instruction to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
132
A/D Clock Period
Conversion Time
(not including acquisition time) (Note 2)
Acquisition Time (Note 3)
Switching Time from Convert  Sample
Discharge Time
A/D CONVERSION TIMING
(Note 2)
Characteristic
9
DD
to AV
8
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
SS
OLD_DATA
or AV
7
SS
. . .
SAMPLING STOPPED
to AV
CY
is added before the A/D clock starts.
CY
DD
. . .
131
130
cycle.
). The source impedance (R
Min
0.7
1.4
1.4
0.2
11
2
(Note 4)
25.0
25.0
Max
12
1
3
1
(1)
(1)
Units
T
s
s
s
s
s
s
AD
0
 2010 Microchip Technology Inc.
T
V
T
A/D RC mode
V
A/D RC mode
-40C to +85C
OSC
OSC
DD
DD
S
AD
) on the input channels is
= 2.0V;
= 2.0V;
based, V
based, V
clock divider.
NEW_DATA
DONE
Conditions
T
CY
REF
REF
 3.0V
full range

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