PIC18LF1330-I/SO Microchip Technology, PIC18LF1330-I/SO Datasheet - Page 140
![IC PIC MCU FLASH 4KX16 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC18LF1330-I/SO
Manufacturer Part Number
PIC18LF1330-I/SO
Description
IC PIC MCU FLASH 4KX16 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
6.PIC18F1230-IP.pdf
(312 pages)
Specifications of PIC18LF1330-I/SO
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
256Byte
Cpu Speed
40MHz
No.
RoHS Compliant
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF1330-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- AC162078 PDF datasheet #2
- PIC18F1230-ISO PDF datasheet #3
- PIC18F1230-ISO PDF datasheet #4
- PIC18F1230-ISO PDF datasheet #5
- PIC18F1230-IP PDF datasheet #6
- Current page: 140 of 312
- Download datasheet (6Mb)
PIC18F1230/1330
13.13 PWM Update Lockout
For a complex PWM application, the user may need to
write up to four Duty Cycle registers and the PWM Time
Base Period Register, PTPER, at a given time. In some
applications, it is important that all buffer registers be
written before the new duty cycle and period values are
loaded for use by the module.
A PWM update lockout feature may optionally be
enabled so the user may specify when new duty cycle
buffer values are valid. The PWM update lockout
feature is enabled by setting the control bit, UDIS, in
the PWMCON1 register. This bit affects all Duty Cycle
Buffer registers and the PWM Time Base Period
register, PTPER.
To perform a PWM update lockout:
1.
2.
3.
4.
13.14 PWM Special Event Trigger
The PWM module has a Special Event Trigger
capability
synchronized to the PWM time base. The A/D sampling
and conversion time may be programmed to occur at
any point within the PWM period. The Special Event
Trigger allows the user to minimize the delay between
the time when A/D conversion results are acquired and
the time when the duty cycle value is updated.
The PWM 16-bit Special Event Trigger register,
SEVTCMP (high and low), and five control bits in the
PWMCON1 register are used to control its operation.
DS39758C-page 138
Set the UDIS bit.
Write all Duty Cycle registers and PTPER, if
applicable.
Clear the UDIS bit to re-enable updates.
With this, when UDIS bit is cleared, the buffer
values will be loaded to the actual registers. This
makes a synchronous loading of the registers.
that
allows
A/D
conversions
Advance Information
to
be
The PTMR value for which a Special Event Trigger
should occur is loaded into the SEVTCMP register pair.
SEVTDIR bit in PWMCON1 register specifies the
counting phase when the PWM time base is in a
Continuous Up/Down Count mode.
If the SEVTDIR bit is cleared, the Special Event Trigger
will occur on the upward counting cycle of the PWM
time base. If SEVTDIR is set, the Special Event Trigger
will occur on the downward count cycle of the PWM
time base. The SEVTDIR bit only effects this operation
when the PWM timer is in the Continuous Up/Down
Count mode.
13.14.1
The PWM module will always produce Special Event
Trigger pulses. This signal may optionally be used by
the A/D module. Refer to Chapter 15.0 "10-Bit
Analog-to-Digital Converter (A/D) Module" for
details.
13.14.2
The PWM Special Event Trigger has a postscaler that
allows a 1:1 to 1:16 postscale ratio. The postscaler is
configured by writing the SEVOPS3:SEVOPS0 control
bits in the PWMCON1 register.
The Special Event Trigger output postscaler is cleared
on any write to the SEVTCMP register pair, or on any
device Reset.
Note:
The Special Event Trigger will take place
only for non-zero values in the SEVTCMP
registers.
SPECIAL EVENT TRIGGER ENABLE
SPECIAL EVENT TRIGGER
POSTSCALER
© 2007 Microchip Technology Inc.
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