PIC18LF1330-I/SO Microchip Technology, PIC18LF1330-I/SO Datasheet - Page 83
![IC PIC MCU FLASH 4KX16 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC18LF1330-I/SO
Manufacturer Part Number
PIC18LF1330-I/SO
Description
IC PIC MCU FLASH 4KX16 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
6.PIC18F1230-IP.pdf
(312 pages)
Specifications of PIC18LF1330-I/SO
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
256Byte
Cpu Speed
40MHz
No.
RoHS Compliant
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF1330-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- AC162078 PDF datasheet #2
- PIC18F1230-ISO PDF datasheet #3
- PIC18F1230-ISO PDF datasheet #4
- PIC18F1230-ISO PDF datasheet #5
- PIC18F1230-IP PDF datasheet #6
- Current page: 83 of 312
- Download datasheet (6Mb)
9.0
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
• LAT register (Output Latch register)
The Output Latch (LAT register) is useful for read-
modify-write operations on the value that the I/O pins
are driving.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 9-1.
FIGURE 9-1:
9.1
PORTA is an 8-bit wide, bidirectional port. The
corresponding Data Direction register is TRISA. Setting
a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISA bit (= 0)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).
© 2007 Microchip Technology Inc.
device)
Note 1:
RD LAT
Data
Bus
WR LAT
or Port
WR TRIS
RD TRIS
RD Port
I/O PORTS
PORTA, TRISA and LATA Registers
I/O pins have diode protection to V
TRIS Latch
Data Latch
D
D
CK
CK
GENERIC I/O PORT
OPERATION
Q
Q
Q
EN
EN
D
DD
and V
Advance Information
I/O pin
Input
Buffer
SS
.
(1)
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The Output Latch (LATA) register is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
Pins RA6 and RA7 are multiplexed with the main
oscillator pins; they are enabled as oscillator or I/O pins
by the selection of the main oscillator in the Configura-
tion register (see Section 19.1 “Configuration Bits”
for details). When they are not used as port pins, RA6
and RA7 and their associated TRIS and LAT bits are
read as ‘0’.
The RA0 pin is multiplexed with one of the analog
inputs, one of the external interrupt inputs, one of the
interrupt-on-change inputs and one of the analog
comparator inputs to become RA0/AN0/INT0/KBI0/
CMP0 pin.
The RA1 pin is multiplexed with one of the analog
inputs, one of the external interrupt inputs and one of
the interrupt-on-change inputs to become RA1/AN1/
INT1/KBI1 pin.
Pins RA2 and RA3 are multiplexed with the Enhanced
USART transmission and reception input (see
Section 19.1 “Configuration Bits” for details).
The RA4 pin is multiplexed with the Timer0 module
clock input, one of the analog inputs and the analog
V
The Fault detect input for PWM FLTA is multiplexed with
pins RA5 and RA7. Its placement is decided by clearing
or setting the FLTAMX bit of Configuration Register 3H.
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 9-1:
CLRF
CLRF
MOVLW
MOVWF
MOVWF
MOVWF
MOVLW
MOVWF
REF
Note:
+ input to become the RA4/T0CKI/AN2/V
PIC18F1230/1330
PORTA
LATA
07h
ADCON1 ; for digital inputs
07h
CMCON
0CFh
TRISA
On a Power-on Reset, RA0, RA1, RA4
and RA5 are configured as analog inputs
and read as ‘0’. RA2 and RA3 are
configured as digital inputs.
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; Configure comparators
; for digital input
; Value used to
; initialize data
; direction
; Set RA<7:6,3:0> as inputs
; RA<5:4> as outputs
INITIALIZING PORTA
DS39758C-page 81
REF
+ pin.
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