ATXMEGA16A4-CU Atmel, ATXMEGA16A4-CU Datasheet - Page 237

• Manufacturer Part Number: ATXMEGA16A4-CU
• Description: MCU AVR 16+4KB FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA16A4-CU

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• Processor Series: ATXMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 5
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 12-bit
• On-chip Dac: 2-ch x 12-bit
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3
21.3.1
8077H–AVR–12/09
Clock Generation
Internal Clock Generation - The Fractional Baud Rate Generator
The clock used for baud rate generation, and for shifting and sampling data bits is generated
internally by the Fractional Baud Rate Generator or externally from the Transfer Clock (XCK)
pin. Five modes of clock generation are supported: Normal and Double Speed asynchronous
mode, Master and Slave synchronous mode, and Master SPI mode.
Figure 21-2. Clock Generation Logic, Block Diagram.I
The Fractional Baud Rate Generator is used for internal clock generation for asynchronous
modes, synchronous master mode, and SPI master mode operation. The generated output fre-
quency (f
Peripheral Clock frequency (f
baud rate (in bits per second) and for calculating the BSEL value for each mode of operation.
BSEL can be set to any value between 0 and 4095. It also show the maximum baud rate versus
peripheral clock speed.
Fractional baud rate generation can be used in asynchronous mode of operation to increase the
average resolution. A scale factor (BSCALE) allows the baud rate to be optionally left or right
scaled. Choosing a positive scale value will results in right scaling, which increase the period
and consequently reduce the frequency of the produced baud rate, without changing the resolu-
tion. If the scale value is negative the divider uses fractional arithmetic counting to increase the
resolution by distributing the fractional divide value over time. BSCALE can be set to any value
from -7 to +7, where 0 implies no scaling. There is a limit to how high the scale factor can be and
the value 2
see
PORT_INV
DDR_XCK
XCK
Pin
Section 21.9 on page 246
BAUD
BSCALE
xcko
xcki
) is given by the period setting (BSEL), an optional scale setting (BSACLE) and the
f
OSC
must be at least half of the minimum number of clock cycles a frame takes,
Baud Rate
Generator
Register
BSEL
Sync
PER
for more details.
).
f
BAUD
Table 21-1 on page 238
Detector
Edge
/2
/4
contains equations for calculating the
/2
DDR_XCK
CLK2X
XMEGA A
0
1
0
1
0
1
1
0
UMSEL [1]
txclk
rxclk
237