ATXMEGA16A4-CU Atmel, ATXMEGA16A4-CU Datasheet - Page 324

• Manufacturer Part Number: ATXMEGA16A4-CU
• Description: MCU AVR 16+4KB FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA16A4-CU

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• Processor Series: ATXMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 5
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 12-bit
• On-chip Dac: 2-ch x 12-bit
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.10.6
26.10.7
8077H–AVR–12/09
STATUS – DAC Status Register
CH0DATAH – DAC Channel 0 Data Register High
Table 26-5.
The number of clock cycles selected multiplied with the period of the Peripheral clock gives the
DAC refresh time.
• Bits 7:2 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 - CH1DRE: DAC Channel 1 Data Register Empty
This bit indicates that the data register for channel 1 is empty, meaning that a new conversion
value may be written. If the bit is cleared, writing to the data register may cause losing a conver-
sion value. This bit is directly used for DMA Request.
• Bit 0 - CH0DRE: DAC Channel 0 Data register Empty
This bit indicates that the data register for channel 0 is empty, meaning that a new conversion
value may be written. If the bit is cleared, writing to the data register may cause losing a conver-
sion value.This bit is directly used for DMA Request.
The two registers CHnDATAH and CHnDATAL are the high byte and low byte respectively of the
12-bit value CHnDATA that is converted to an analog voltage on DAC channel n. By default, the
12 bits are distributed with 8 bits in CHnDATAL and 4 bits in 4 LSB position of CHnDATAH
(right-adjusted).To select left-adjusted data it is possible by setting the LEFTADJ bit in the
CTRLC register.
When this is selected, it is also possible to do 8-bit conversions by writing only CHnDATAH
register.
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Bit
+0x05
Read/Write
Initial Value
1101
1110
1111
R
7
0
-
DAC Channel refresh control selection (Continued)
Bit
+0x19
Read/Write
Read/Write
Initial Value
Initial Value
R
6
0
-
7
R/W
R
0
0
-
R
5
0
OFF
-
6
R/W
R
0
0
-
R
4
0
-
5
R/W
R
0
0
-
R
3
0
-
4
R/W
R
0
0
CHDATA[11:4]
-
R
2
0
-
3
R/W
R/W
Auto refresh off
0
0
Reserved
Reserved
CH1DRE
R/W
2
1
0
R/W
R/W
0
0
CHDATA[11:8]
XMEGA A
CH0DRE
1
R/W
0
0
R/W
R/W
0
0
STATUS
0
R/W
R/W
0
0
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