ATXMEGA16A4-CU Atmel, ATXMEGA16A4-CU Datasheet - Page 34

• Manufacturer Part Number: ATXMEGA16A4-CU
• Description: MCU AVR 16+4KB FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA16A4-CU

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• Processor Series: ATXMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 5
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 12-bit
• On-chip Dac: 2-ch x 12-bit
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8077H–AVR–12/09
Table 4-8.
• Bit 5:4 - BLBA[1:0]: Boot Lock Bit Application Section
These bits indicate the locking mode for the Application Section. Even though the BLBA bits are
writable, they can only be written to a stricter locking. Resetting the BLBA bits is only possible by
executing a Chip Erase Command.
Table 4-9.
BLBB[1:0]
BLBA[1:0]
11
10
01
00
11
10
01
00
Boot Lock Bit for The Boot Loader Section
Boot Lock Bit for the Application Section
Group Configuration
Group Configuration
RWLOCK
RWLOCK
NOLOCK
NOLOCK
WLOCK
WLOCK
RLOCK
RLOCK
Description
No Lock, no restrictions for SPM and (E)LPM accessing
the Boot Loader section.
Write Lock, SPM is not allowed to write the Boot Loader
section
Read Lock, (E)LPM executing from the Application
section is not allowed to read from the Boot Loader
section.
If the interrupt vectors are placed in the Application
section, interrupts are disabled while executing from the
Boot Loader section.
Read and Write Lock, SPM is not allowed to write to the
Boot Loader section and (E)LPM executing from the
Application section is not allowed to read from the Boot
Loader section.
If the interrupt vectors are placed in the Application
section, interrupts are disabled while executing from the
Boot Loader section
Description
No Lock, no restrictions for SPM and (E)LPM accessing
the Application Section.
Write Lock, SPM is not allowed to write them
Application Section
Read Lock, (E)LPM executing from the Boot Loader
Section is not allowed to read from the Application
Section.
If the interrupt vectors are placed in the Boot Loader
Section, interrupts are disabled while executing from the
Application Section.
Read and Write Lock, SPM is not allowed to write to the
Application Section and (E)LPM executing from the
Boot Loader Section is not allowed to read from the
Application section.
If the interrupt vectors are placed in the Boot Loader
Section, interrupts are disabled while executing from the
Application Section.
XMEGA A
34