PIC18F2431-I/SO Microchip Technology, PIC18F2431-I/SO Datasheet - Page 177

• Manufacturer Part Number: PIC18F2431-I/SO
• Description: IC PIC MCU FLASH 8KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2431-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/SPI/SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILI3-DB18F4431 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 16-11:
16.2.6
The velocity pulse generator, in conjunction with the
IC1 and the synchronous TMR5 (in synchronous
operation), provides a method for high accuracy speed
measurements at both low and high mechanical motor
speeds. The Velocity mode is enabled when the VELM
bit is cleared (= 0) and QEI is set to one of its operating
modes (see Table 16-6).
To optimize register space, the input capture channel
one (IC1) is used to capture TMR5 counter values.
Input capture buffer register, CAP1BUF, is redefined in
Velocity Measurement mode, VELM = 0, as the
Velocity Register buffer (VREGH, VREGL).
 2003 Microchip Technology Inc.
Note 1: POSCNT register is shown in QEI x4 Update mode (POSCNT increments on every rising and every falling edge of
2: When INDX Reset pulse is detected, POSCNT is reset to ‘
3: IC2QEI is enabled for one T
4: Position counter is loaded with ‘0000h’ (i.e., Reset) on the next QEA or QEB edge when INDX is high.
5: Position counter is loaded with MAXCNT value (e.g., 1527h) on the next QEA or QEB edge following the INDX
6: IC2QEIF must be cleared in software.
QEA
QEB
count (+/-)
POSCNT
MAXCNT
INDX
IC2QEIF
UP/DOWN
VELOCITY MEASUREMENT
Position
counter load
QEA and QEB input signals)
MAXCNT when POSCNT = 0 (when decrementing), which occurs on the next QEA or QEB edge. Similar Reset
sequence occurs for the reverse direction except that the INDX signal is recognized on its falling edge. The Reset
is generated on the next QEA or QEB edge.
falling edge input signal detect).
(1)
QEI MODULE RESET TIMING WITH THE INDEX INPUT
+1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1
MAXCNT=1527
CY
Note 2
Q1
Q4
clock cycle.
Forward
(4)
(3)
PIC18F2331/2431/4331/4431
Note 6
Preliminary
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
Note 2
Q1
TABLE 16-6:
Q4
QEIM<2:0>
(5)
0
(3)
’ on the next QEA or QEB edge. POSCNT is set to
001
010
101
110
Reverse
x2 Velocity Event mode. The velocity
pulse is generated on every QEA
edge.
x4 Velocity Event mode. The velocity
pulse is generated on every QEA and
QEB active edge.
VELOCITY PULSES
Velocity Event Mode
DS39616B-page 175