PIC18F2431-I/SO Microchip Technology, PIC18F2431-I/SO Datasheet - Page 221

• Manufacturer Part Number: PIC18F2431-I/SO
• Description: IC PIC MCU FLASH 8KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2431-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/SPI/SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILI3-DB18F4431 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 18-6:
18.3.1.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin SCK/SCL is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then,
pin SCK/SCL should be enabled by setting bit CKP
(SSPCON<4>). The master must monitor the SCL pin
prior to asserting another clock pulse. The slave
devices may be holding off the master by stretching the
clock. The eight data bits are shifted out on the falling
edge of the SCL input. This ensures that the SDA signal
is valid during the SCL high time (Figure 18-7).
FIGURE 18-7:
 2003 Microchip Technology Inc.
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S
S
A7 A6 A5 A4 A3 A2 A1
1
Transmission
A7
2
1
Data in
sampled
Receiving Address
3
A6
2
I
I
4
2
2
C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
A5
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address
3
5
A4
6
4
7
A3
5
R/W = 0
8
A2
6
ACK
9
A1
7
D7
1
PIC18F2331/2431/4331/4431
D6
R/W = 1
2
8
SSPBUF register is read
Preliminary
Receiving Data
D5
3
Cleared in software
9
ACK
responds to SSPIF
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
while CPU
SCL held low
D3
5
D2
6
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the data transfer is complete. When the ACK is latched
by the slave, the slave logic is reset (resets SSPSTAT
register) and the slave then monitors for another
occurrence of the Start bit. If the SDA line was low
(ACK), the transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR
register. Then pin SCK/SCL should be enabled by
setting bit CKP.
D1
7
D7
1
SSPBUF is written in software
D0
8
ACK
9
D6
2
Cleared in software
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
D7
1
D5
3
D6
2
D4
4
D5
Receiving Data
3
Transmitting Data
D3
D4
4
5
ACK is not sent.
D3
D2
5
6
D2
6
From SSP Interrupt
Service Routine
D1
7
D1
7
D0
DS39616B-page 219
8
D0
8
ACK
ACK
9
9
transfer
Bus Master
terminates
P
P