PIC18F2431-I/SO Microchip Technology, PIC18F2431-I/SO Datasheet - Page 285

• Manufacturer Part Number: PIC18F2431-I/SO
• Description: IC PIC MCU FLASH 8KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2431-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/SPI/SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILI3-DB18F4431 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro
The user program memory is divided into five blocks.
One of these is a boot block of 512 bytes. The
remainder of the memory is divided into four blocks on
binary boundaries.
FIGURE 22-5:
TABLE 22-3:
 2003 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend:
Unimplemented
File Name
(PIC18FX331)
Program Verification and
Code Protection
®
Boot Block
devices.
8 Kbytes
Read 0’s
Shaded cells are unimplemented.
Block 0
Block 1
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
SUMMARY OF CODE PROTECTION REGISTERS
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2331/2431/4331/4431
WRTD
0000h
0FFFh
0200h
0FFFh
1000h
1FFFh
3FFFh
Bit 7
CPD
Address
—
—
—
—
Range
EBTRB
WRTB
Bit 6
CPB
—
—
—
PIC18F2331/2431/4331/4431
(PIC18FX431)
MEMORY SIZE/DEVICE
Boot Block
16 Kbytes
Block 0
Block 1
Block 2
Block 3
Preliminary
WRTC
Bit 5
—
—
—
—
—
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 22-5 shows the program memory organization
for 8- and 16-Kbyte devices, and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 22-3.
Bit 4
—
—
—
—
—
—
0000h
01FFh
0200h
0FFFh
1000h
1FFFh
2000h
2FFFh
3000h
3FFFh
Address
Range
EBTR3
WRT3
Bit 3
CP3
—
—
—
Block Code Protection
EBTR2
WRT2
Bit 2
CPB, WRTB, EBTRB
CP2
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
—
—
—
Controlled By:
EBTR1
WRT1
Bit 1
CP1
DS39616B-page 283
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—