AT89C51RE2-SLRUM Atmel, AT89C51RE2-SLRUM Datasheet - Page 158

• Manufacturer Part Number: AT89C51RE2-SLRUM
• Description: MCU 8051 128K FLASH 44-PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RE2-SLRUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89OCD-01
• For Use With: AT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Serial Peripheral Status
Register and Control
(SPSCR)
158
AT89C51RE2
Reset Value = 0001 0100b
Not bit addressable
The Serial Peripheral Status Register contains flags to signal the following conditions:
•
•
•
Table 116. SPSCR Register
SPSCR - Serial Peripheral Status and Control register (C4H)
Bit Number
Bit Number
SPIF
Data transfer complete
Write collision
Inconsistent logic level on SS pin (mode fault error)
7
7
6
5
3
2
1
0
Mnemonic
SPIF
OVR
Bit
6
-
-
Bit Mnemonic
CPHA
CPOL
SPR1
SPR0
Description
Serial Peripheral Data Transfer Flag
Cleared by hardware to indicate data transfer is in progress or has been approved by a
clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
This bit is cleared when reading or writing SPDATA after reading SPSCR.
Reserved
Overrun Error Flag
- Set by hardware when a byte is received whereas SPIF is set (the previous received
data is not overwritten).
- Cleared by hardware when reading SPSCR
OVR
5
The value read from this bit is indeterminate. Do not set this bit.
Description
Clock Polarity
Cleared to have the SCK set to’0’ in idle state.
Set to have the SCK set to’1’ in idle state.
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle state (see
CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
SPR2
0
0
0
0
1
1
1
1
MODF
4
SPR1
0
0
1
1
0
0
1
1
SPR0 Serial Peripheral Rate
0
1
0
1
0
1
0
1
SPTE
3
F
F
Invalid
F
F
F
F
Invalid
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
UARTM
/16
/32
2
/4
/8
/64
/128
SPTEIE
1
7663E–8051–10/08
MODFIE
0