AT89C51RE2-SLRUM Atmel, AT89C51RE2-SLRUM Datasheet - Page 53

MCU 8051 128K FLASH 44-PLCC

AT89C51RE2-SLRUM

Manufacturer Part Number
AT89C51RE2-SLRUM
Description
MCU 8051 128K FLASH 44-PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51RE2-SLRUM

Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
34
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89OCD-01
For Use With
AT89STK-11 - KIT STARTER FOR AT89C51RX2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

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Manufacturer
Quantity
Price
Part Number:
AT89C51RE2-SLRUM
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Part Number:
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Bootloader Architecture
Introduction
7663E–8051–10/08
Specific Protocol
External Host with
Communication
The bootloader manages a communication between a host platform running an ISP tool and a
AT89C51RE2 target.
The bootloader implemented in AT89C51RE2 is designed to reside in the dedicated ROM bank.
This memory area can only be executed (fetched) when the processor enters the boot process.
The implementation of the bootloader is based on standard set of libraries including INTEL hex
based protocol, standard communication links and ATMEL ISP command set.
Figure 19. Bootloader Functional Description
On the above diagram, the on-chip bootloader processes are:
The purpose of this process is to manage the communication and its protocol between the on-
chip bootloader and a external device. The on-chip ROM implement a serial protocol (see sec-
tion Bootloader Protocol). This process translate serial communication frame (UART) into Flash
memory access (read, write, erase...).
This process manages low level access to Flash memory (performs read and write access).
ISP Communication Management
Memory Management
ISP Communication
Management
Management
Memory
Memory
Bootloader
AT89C51RE2
53

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