AT89C51RE2-SLRUM Atmel, AT89C51RE2-SLRUM Datasheet - Page 52
AT89C51RE2-SLRUM
Manufacturer Part Number
AT89C51RE2-SLRUM
Description
MCU 8051 128K FLASH 44-PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51RE2-SLSUM.pdf
(187 pages)
Specifications of AT89C51RE2-SLRUM
Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
34
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89OCD-01
For Use With
AT89STK-11 - KIT STARTER FOR AT89C51RX2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51RE2-SLRUM
Manufacturer:
Atmel
Quantity:
759
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Flash Protection from Parallel Programming
52
AT89C51RE2
The three lock bits in Hardware Security Byte (see "In-System Programming" section) are pro-
grammed according to Table 32 provide different level of protection for the on-chip flash memory
FM0.
They are set by default to level 4
Table 32. Program Lock Bit FLB2-0
Program Lock bits
U: unprogrammed
P: programmed
WARNING: Security level 2 and 3 should only be programmed after verification.
Security
level
1
2
3
4
Program Lock Bits
FLB0
U
U
U
P
FLB1
U
U
P
U
FLB2
U
U
U
P
Protection Description
No program lock features enabled.
MOVC instruction executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on reset,
and further parallel programming of the Flash is disabled.
ISP allows only flash verification (no write operations are allowed) but IAP from
internal code still allowed.
Same as 2, also verify through parallel programming interface is disabled and
ISP read operation not allowed.
Same as 3, also external execution is disabled (external bank not accessible)
7663E–8051–10/08
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