AT89C51RE2-SLRUM Atmel, AT89C51RE2-SLRUM Datasheet - Page 41

• Manufacturer Part Number: AT89C51RE2-SLRUM
• Description: MCU 8051 128K FLASH 44-PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RE2-SLRUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89OCD-01
• For Use With: AT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Loading the Column
Latches
7663E–8051–10/08
Any number of data from 0 byte to 128 bytes can be loaded in the column latches. The data writ-
ten in the column latches can be written in a none consecutive order. The DPTR allows to select
the address of the byte to load in the column latches.
The page address to be written (target page in FM0) is given by the last address loaded in the
column latches and when this page belongs to the upper 32K bytes of the logical addressable
MCU space, the target memory bank selection is performed upon the MBO2:0 value during the
last address loaded.
When 0 byte is loaded in the column latches the activation sequence (5xh, Axh in FCON) does
not launch any operations. The FSE bit in FSTA register is set.
When a current flash write operation is on-going (FBUSY is set), it is impossible to load the col-
umns latches before the end of flash programming process (the write operation in the columns
latches is not performed, and the previous columns latches content is not overwritten).
When programming is launched, an automatic erase of the entire memory page is first per-
formed, then programming is effectively done. Thus no page or block erase is needed and only
the loaded data are programmed in the corresponding page. The unloaded data of the target
memory page are programmed at 0xFF value (automatic page erase value).
The following procedure is used to load the column latches and is summarized in Figure 13:
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Disable interrupt and map the column latch space by setting FPS bit.
Select the target memory bank (for page address larger than 32K)
Map the column latch
Reset the column latch
Load the DPTR with the address to write.
Load Accumulator register with the data to write.
Execute the MOVX @DPTR, A instruction, and only this one (no MOVX @Ri, A).
If needed loop the last three instructions until the page is completely loaded.
Unmap the column latch if needed (it can be left mapped) and Enable Interrupt
AT89C51RE2
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