AT89C51RE2-SLRUM Atmel, AT89C51RE2-SLRUM Datasheet - Page 38

• Manufacturer Part Number: AT89C51RE2-SLRUM
• Description: MCU 8051 128K FLASH 44-PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RE2-SLRUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89OCD-01
• For Use With: AT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

FSTA Register
38
AT89C51RE2
Table 24. FSTA Register
FSTA Register (S:D3h)
Flash Status Register
Reset Value= ‘R’xxx x000b
Where ‘R’ depends on the reset conditions: If RM0 is executed after Reset R=1, if FM0 is exe-
cuted after reset R=0
Bit Number
FMR
6-3
7
7
2
1
0
Mnemonic
FLOAD
FBUSY
FMR
FSE
Bit
6
-
-
Description
Flash Movc Redirection
When code is executed from RM0 (and only RM0), this bit allow the MOVC instruction to
be redirected to FM0.
Clear this bit to allow MOVC instruction to read FM0
Set this bit to allow MOVC instruction to read RM0
This bit can be written only from RM0 (on-chip ROM bootloader execution).
unused
Flash sequence error
Set by hardware when the flash activation sequencers FCON 5X and MOV FCON AX) is
not correct (See Error Report Section)
Clear by software or clear by hardware if the last activation sequence was correct
(previous error is canceled)
Flash Columns latch loaded
Set by hardware when the first data is loaded in the column latches.
Clear by hardware when the activation sequence succeeds (flash write success, or reset
column latch success)
Flash Busy
Set by hardware when programming is in progress.
Clear by hardware when programming is done.
Can not be changed by software.
5
-
4
-
3
-
FSE
2
FLOAD
1
7663E–8051–10/08
FBUSY
0