PIC18F4580-I/P Microchip Technology, PIC18F4580-I/P Datasheet - Page 339

• Manufacturer Part Number: PIC18F4580-I/P
• Description: IC PIC MCU FLASH 16KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580-I/P

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 23-6:
FIGURE 23-7:
23.11 Programming Time Segments
Some requirements for programming of the time
segments:
• Prop_Seg + Phase_Seg 1 ≥ Phase_Seg 2
• Phase_Seg 2 ≥ Sync Jump Width.
For example, assume that a 125 kHz CAN baud rate is
desired, using 20 MHz for F
a baud rate prescaler value of 04h gives a T
To obtain a Nominal Bit Rate of 125 kHz, the Nominal
Bit Time must be 8 μs or 16 T
Using 1 T
and 7 T
point at 10 T
Phase Segment 2.
By the rules above, the Sync Jump Width could be the
maximum of 4 T
only necessary when the clock generation of the
different nodes is inaccurate or unstable, such as using
ceramic resonators. Typically, an SJW of 1 is enough.
© 2007 Microchip Technology Inc.
Input
Signal
Bit
Time
Segments
T
Q
T
Q
Q
for Phase Segment 1 would place the sample
Q
for the Sync_Seg, 2 T
Q
Sync
after the transition. This leaves 6 T
Sync
Q
. However, normally a large SJW is
LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1)
SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2)
Segment
Segment
Prop
OSC
Prop
Q
.
. With a T
Q
for the Prop_Seg
Nominal Bit Length
OSC
Actual Bit Length
Q
Segment 1
of 500 ns.
PIC18F2480/2580/4480/4580
of 50 ns,
Segment 1
Phase
Phase
Q
Preliminary
for
Nominal Bit Length
Actual Bit Length
Sample Point
23.12 Oscillator Tolerance
As a rule of thumb, the bit timing requirements allow
ceramic resonators to be used in applications with
transmission rates of up to 125 Kbit/sec. For the full bus
speed range of the CAN protocol, a quartz oscillator is
required. A maximum node-to-node oscillator variation
of 1.7% is allowed.
≤ SJW
Sample Point
Segment 2
Phase
Segment 2
Phase
DS39637C-page 337
≤ SJW