PIC18F4580-I/P Microchip Technology, PIC18F4580-I/P Datasheet - Page 476

• Manufacturer Part Number: PIC18F4580-I/P
• Description: IC PIC MCU FLASH 16KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580-I/P

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2480/2580/4480/4580
Timer1 .............................................................................. 151
Timer2 .............................................................................. 157
Timer3 .............................................................................. 159
Timing Diagrams
DS39637C-page 474
16-Bit Mode Reads and Writes ................................ 148
Associated Registers ............................................... 149
Clock Source Edge Select (T0SE Bit) ...................... 148
Clock Source Select (T0CS Bit) ............................... 148
Operation ................................................................. 148
Overflow Interrupt .................................................... 149
Prescaler. See Prescaler, Timer0.
16-Bit Read/Write Mode ........................................... 153
Associated Registers ............................................... 155
Interrupt .................................................................... 154
Operation ................................................................. 152
Oscillator .......................................................... 151, 153
Oscillator Layout Considerations ............................. 154
Overflow Interrupt .................................................... 151
Resetting, Using a Special Event Trigger
Special Event Trigger (ECCP) ................................. 174
TMR1H Register ...................................................... 151
TMR1L Register ....................................................... 151
Use as a Real-Time Clock ....................................... 154
Associated Registers ............................................... 158
Interrupt .................................................................... 158
Operation ................................................................. 157
Output ...................................................................... 158
PR2 Register .................................................... 169, 175
TMR2 to PR2 Match Interrupt .......................... 169, 175
16-Bit Read/Write Mode ........................................... 161
Associated Registers ............................................... 161
Operation ................................................................. 160
Oscillator .......................................................... 159, 161
Overflow Interrupt ............................................ 159, 161
Special Event Trigger (CCP) .................................... 161
TMR3H Register ...................................................... 159
TMR3L Register ....................................................... 159
A/D Conversion ........................................................ 450
Acknowledge Sequence .......................................... 220
Asynchronous Reception ......................................... 239
Asynchronous Transmission .................................... 237
Asynchronous Transmission
Automatic Baud Rate Calculation ............................ 235
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 240
Baud Rate Generator with Clock Arbitration ............ 214
BRG Overflow Sequence ......................................... 235
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ........................................... 436
Bus Collision During a Repeated
Bus Collision During a Repeated
Bus Collision During a Start
Bus Collision During a Start
Bus Collision During a Stop
Bus Collision During a Stop
Output (CCP) ................................................... 154
(Back-to-Back) ................................................. 237
Normal Operation ............................................. 240
During Start Condition ...................................... 223
Start Condition (Case 1) .................................. 224
Start Condition (Case 2) .................................. 224
Condition (SCL = 0) ......................................... 223
Condition (SDA only) ....................................... 222
Condition (Case 1) ........................................... 225
Condition (Case 2) ........................................... 225
Preliminary
Bus Collision for Transmit and Acknowledge .......... 221
Capture/Compare/PWM (CCP) ............................... 438
CLKO and I/O .......................................................... 435
Clock Synchronization ............................................. 207
EUSART Synchronous Receive (Master/Slave) ...... 448
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 440
Example SPI Master Mode (CKE = 1) ..................... 441
Example SPI Slave Mode (CKE = 0) ....................... 442
Example SPI Slave Mode (CKE = 1) ....................... 443
External Clock (All Modes except PLL) ................... 433
Fail-Safe Clock Monitor ........................................... 356
First Start Bit Timing ................................................ 215
Full-Bridge PWM Output .......................................... 179
Half-Bridge PWM Output ......................................... 178
High/Low-Voltage Detect (VDIRMAG = 0) ............... 269
High/Low-Voltage Detect (VDIRMAG = 1) ............... 270
I
I
I
I
I
I
I
I
I
I
I
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4480/4580) ................... 439
Parallel Slave Port (PSP) Read ............................... 145
Parallel Slave Port (PSP) Write ............................... 145
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 181
PWM Direction Change at Near
PWM Output ............................................................ 169
Repeat Start Condition ............................................ 216
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 241
Slave Synchronization ............................................. 193
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 192
SPI Mode (Slave Mode with CKE = 0) ..................... 194
SPI Mode (Slave Mode with CKE = 1) ..................... 194
Stop Condition Receive or Transmit Mode .............. 220
Synchronous Reception (Master Mode, SREN) ...... 244
Synchronous Transmission ..................................... 242
Synchronous Transmission (Through TXEN) .......... 243
Time-out Sequence on POR w/ PLL
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 444
C Bus Start/Stop Bits ............................................ 444
C Master Mode (7 or 10-Bit Transmission) ........... 218
C Master Mode (7-Bit Reception) .......................... 219
C Slave Mode (10-Bit Reception, SEN = 0) .......... 204
C Slave Mode (10-Bit Reception, SEN = 1) .......... 209
C Slave Mode (10-Bit Transmission) .................... 205
C Slave Mode (7-Bit Reception, SEN = 0) ............ 202
C Slave Mode (7-Bit Reception, SEN = 1) ............ 208
C Slave Mode (7-Bit Transmission) ...................... 203
C Slave Mode General Call Address
(Master/Slave) ................................................. 448
Sequence (7 or 10-Bit Address Mode) ............ 210
Auto-Restart Disabled) .................................... 184
Auto-Restart Enabled) ..................................... 184
100% Duty Cycle ............................................. 181
Timer (OST) and Power-up Timer (PWRT) ..... 436
V
Enabled (MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
DD
Rise > T
2
2
C Bus Data ........................................ 446
C Bus Start/Stop Bits ........................ 446
PWRT
© 2007 Microchip Technology Inc.
DD
) ............................................ 47
, V
DD
DD
DD
), Case 1 ...................... 46
), Case 2 ...................... 46
Rise T
DD
DD
) ............................ 47
,
PWRT
) .............. 46