PIC18F4580-I/P Microchip Technology, PIC18F4580-I/P Datasheet - Page 81

• Manufacturer Part Number: PIC18F4580-I/P
• Description: IC PIC MCU FLASH 16KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580-I/P

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 5-2:
© 2007 Microchip Technology Inc.
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEDATA
EECON2
EECON1
IPR3
Mode 0
IPR3
Mode 1, 2
PIR3
Mode 0
PIR3
Mode 1, 2
PIE3
Mode 0
PIE3
Mode 1, 2
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISE
TRISD
TRISC
TRISB
TRISA
LATE
LATD
LATC
LATB
LATA
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1:
File Name
(3)
(3)
2:
3:
4:
5:
6:
7:
8:
9:
(3)
(3)
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices;
individual unimplemented bits should be interpreted as ‘—’.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
CAN bits have multiple functions depending on the selected mode of the CAN module.
This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
These registers are available on PIC18F4X80 devices only.
EUSART Baud Rate Generator High Byte
EUSART Baud Rate Generator
EUSART Receive Register
EUSART Transmit Register
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
PORTD Data Direction Register
PORTC Data Direction Register
PORTB Data Direction Register
LATD Output Latch Register
LATC Output Latch Register
LATB Output Latch Register
TRISA7
PSPIP
PSPIF
PSPIE
LATA7
OSCFIP
OSCFIF
OSCFIE
INTSRC
EEPGD
CSRC
SPEN
IRXIP
IRXIP
IRXIF
IRXIF
IRXIE
IRXIE
Bit 7
IBF
—
REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
(3)
(3)
(3)
(6)
(6)
TRISA6
PLLEN
LATA6
CMIP
CMIE
CMIF
WAKIP
WAKIP
WAKIF
WAKIF
WAKIE
WAKIE
CFGS
ADIP
ADIF
ADIE
Bit 6
OBF
TX9
RX9
—
(9)
(9)
(9)
(6)
(4)
(6)
PORTA Data Direction Register
LATA Output Latch Register
ERRIP
ERRIP
ERRIF
ERRIF
ERRIE
ERRIE
TXEN
SREN
RCIP
RCIF
RCIE
IBOV
Bit 5
—
—
—
—
—
—
PIC18F2480/2580/4480/4580
PSPMODE
TXB2IP
TXBnIP
TXB2IF
TXBnIF
TXB2IE
TXBnIE
SYNC
CREN
FREE
TUN4
EEIP
EEIF
EEIE
Bit 4
TXIP
TXIF
TXIE
—
Preliminary
TXB1IP
TXB1IF
TXB1IE
WRERR
SENDB
ADDEN
TXB1IP
TXB1IE
TXB1IF
BCLIP
BCLIE
SSPIP
SSPIF
SSPIE
BCLIF
TUN3
Bit 3
—
—
(8)
(8)
(8)
TXB0IP
TXB0IE
TXB0IF
HLVDIP
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TRISE2
TXB0IP
TXB0IF
TXB0IE
HLVDIF
WREN
LATE2
BRGH
FERR
TUN2
Bit 2
(8)
(8)
(8)
TMR3IP
TMR3IE
TMR2IP
TMR2IE
RXB1IP
RXBnIP
RXB1IF
RXBnIF
RXB1IE
RXBnIE
TMR3IF
TMR2IF
TRISE1
LATE1
TRMT
OERR
TUN1
Bit 1
WR
ECCP1IP
ECCP1IF
ECCP1IE
FIFOWMIP
FIFOMWIE
FIFOWMIF
RXB0IP
RXB0IE
TMR1IP
TMR1IF
TMR1IE
RXB0IF
TRISE0
LATE0
RX9D
TX9D
TUN0
Bit 0
RD
(9)
(9)
(9)
DS39637C-page 79
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000
0000 0000
0000 0000
xx-0 x000
1111 1111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
11-1 1111
00-0 0000
00-0 0000
1111 1111
0000 0000
0000 0000
0q-0 0000
0000 -111
1111 1111
1111 1111
1111 1111
1111 1111
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
POR, BOR
Value on
Details on
51, 231
51, 231
51, 238
51, 236
51, 237
51, 237
51, 105
51, 105
51, 105
51, 105
51, 126
51, 126
51, 120
51, 120
51, 123
51, 123
51, 125
52, 119
52, 122
52, 124
52, 118
52, 121
52, 141
52, 138
52, 135
52, 132
52, 129
52, 141
52, 138
52, 135
52, 132
52, 129
Page:
27, 52