ATSAM3U2EA-AU Atmel, ATSAM3U2EA-AU Datasheet - Page 345

• Manufacturer Part Number: ATSAM3U2EA-AU
• Description: IC MCU 32BIT 128KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U2EA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 36K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b, 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Controller Family/series: SAM3U
• No. Of I/o's: 96
• Ram Memory Size: 36KB
• Cpu Speed: 96MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 36 KB
• Interface Type: 4xUSART, 2xTWI, 5xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

24.6.1
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in the
• ULBT: Undefined Length Burst Type
0: Infinite Length Burst
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
1: Single Access
The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR
burst.
2: Four Beat Burst
The undefined length burst is split into 4 beats burst allowing rearbitration at each 4 beats burst end.
3: Eight Beat Burst
The undefined length burst is split into 8 beats burst allowing rearbitration at each 8 beats burst end.
4: Sixteen Beat Burst
The undefined length burst is split into 16 beats burst allowing rearbitration at each 16 beats burst end.
6430D–ATARM–25-Mar-11
31
23
15
–
–
–
7
–
Bus Matrix Master Configuration Registers
MATRIX_MCFG0..MATRIX_MCFG4
0x400E0200
Read-write
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
“Write Protect Mode
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
Register”.
SAM3U Series
ULBT
25
17
–
–
9
–
1
24
16
–
–
8
–
0
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