ATSAM3U4EA-CU Atmel, ATSAM3U4EA-CU Datasheet - Page 1155

• Manufacturer Part Number: ATSAM3U4EA-CU
• Description: IC MCU 32BIT 256KB FLSH 144LFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4EA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b, 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 4xUSART, 2xTWI, 5xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, AT91SAM3U-EK, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6430D–ATARM–25-Mar-11
Doc.
Rev.
6430C
Comments (Continued)
RTC:
Section 18.3.2
Section 18.5 ”Real Time Clock (RTC) User
TIMEVSEL, CALEVSEL bitfield descriptions reorganized.
SSC:
Redundant letter C removed from title.
SUPC:
Section 19.4 ”Supply Controller (SUPC) User
FWUPDBC, WUPDBC bitfield descriptions reorganized.
Backup supply is VDDBU
TC:
Figure 36-2 ”Clock Chaining
updated bitfields: TC0XC0S, TC1XC1S, TC2XC2S, TCCLKS, BURST, ETRGEDG, LDRA, LDRB, TCCLKS,
BURST, EEVTEDG, EEVT, WAVSEL, ACPA, ACPC, AEEVT, ASWTRG, BCPB, BCPC, BEEVT, BSWTRG
UDHP:
Figure 39-4 ”Logical Address Space for DPR
Figure 39-1 ”Block
Figure 39.4 ”Product
Figure 39-6 ”Register
USART:
Section 35.6.7 ”Modem
Section 35.6 ”Functional
Section 35.6.8.2 ”Baud Rate”
SPI Master Mode: ...”the value programmed in CD must be superior or equal to 6.”
SPI Slave Mode:...”the external clock (SCK) frequency must be at least 6 times lower than the system clock.”
Section 35.6.1 ”Baud Rate
USART mode, or 6 in SPI mode.”
Section 35.6.1.3 ”Baud Rate in Synchronous Mode or SPI
MCK/3 in USART mode, or MCK/6 in SPI mode.”
”Interrupt”, updated.
Diagram”, 1 PMC to UTMI signal line. Notes removed.
Dependencies”, added to datasheet.
Mapping”, DMA offset updated to 0x300 + channel *...
Mode”, is available.
Description”, ...SCK up to MCK/6
Generator”,”...signal provided on SCK must be at least 3 times lower than MCK in
Selection”, channel 1 updated.
Interface”, the reset for RTC_CALR is 0x01210720.
Access”, EP0 has but 1 bank
Interface”, offset updated for GPBR: 0x90-0xDC.
Mode”, ...”limits the SCK maximum frequency to
SAM3U Series
Change
Request
Ref.
7071
7046/7087
6796
6949
6950
6796
6714
6687
6796
6750
6792
rfo
6822
6791
rfo→ 7097
1155